Comp Arch | BA0DC26B80C69157E694C1B1B68FC10598D24CE3

Comp Arch

Name	Comp Arch	DOWNLOAD Copy Link
Total Size	3.6 GB
Total Files	108
Hash	BA0DC26B80C69157E694C1B1B68FC10598D24CE3

/.../L1 - Instrction Set Architecture/
1 - 1 - L1S1 Course Overview (434) (1).mp4	19.5 MB
1 - 1 - L1S1 Course Overview (434).mp4	19.5 MB
1 - 2 - L1S2 Motivation (1640).mp4	45.4 MB
1 - 3 - L1S3 Course Content (910).mp4	27.0 MB
1 - 4 - L1S4 Architecture and Microarchitecture (2337).mp4	55.4 MB
1 - 5 - L1S5 Machine Models (1602).mp4	34.4 MB
1 - 6 - L1S6 ISA Characteristics (2547).mp4	60.8 MB
1 - 7 - L1S7 Recap (0117).mp4	2.0 MB
/.../L10-Branch Prediction/
10 - 1 - L10S1 Branch Cost Motivation (637).mp4	12.6 MB
10 - 2 - L10S2 Branch Prediction Introduction (518).mp4	9.8 MB
10 - 3 - L10S3 Static Outcome Prediction (1605).mp4	30.8 MB
10 - 4 - L10S4 Dynamic Outcome Prediction (2912).mp4	56.7 MB
10 - 5 - L10S5 Target Address Prediction (1845).mp4	37.5 MB
/.../L11-Advanced Caches 1/
11 - 1 - L11S1 Basic Cache Optimizations (1608).mp4	36.2 MB
11 - 2 - L11S2 Cache Pipelining (1416).mp4	29.8 MB
11 - 3 - L11S3 Write Buffers (952).mp4	22.6 MB
11 - 4 - L11S4 Multilevel Caches (1737).mp4	34.6 MB
11 - 5 - L11S5 Victim Caches (604).mp4	13.9 MB
11 - 6 - L11S6 Prefetching (1234).mp4	26.7 MB
/.../L12-Advanced Caches 2/
12 - 1 - L12S1 Multiporting and Banking (2008).mp4	51.0 MB
12 - 2 - L12S2 Software Memory Optimizations (1653).mp4	74.3 MB
12 - 3 - L12S3 Non-blocking Caches (1929).mp4	44.2 MB
12 - 4 - L12S4 Critical Word First and Early Restart (306).mp4	7.4 MB
/.../L13-Memory Protection/
13 - 1 - L13S1 Memory Management Introduction (1304).mp4	33.6 MB
13 - 2 - L13S2 Base and Bound Registers (1144).mp4	27.3 MB
13 - 3 - L13S3 Page Based Memory Systems (2704).mp4	64.9 MB
13 - 4 - L13S4 Translation and Protection (1437).mp4	35.2 MB
13 - 5 - L13S5 TLB Processing (1200).mp4	27.3 MB
/.../L14-Vector Processors & GPU/
14 - 1 - L14S1 Address Translation Review (936).mp4	23.8 MB
14 - 2 - L14S2 Cache and Memory Protection Interaction (2218).mp4	57.6 MB
14 - 3 - L14S3 Vector Processor Introduction (1804).mp4	46.7 MB
14 - 4 - L14S4 Vector Parallelism (644).mp4	14.5 MB
14 - 5 - L14S5 Vector Hardware Optimizations (1852).mp4	43.8 MB
14 - 6 - L14S6 Vector Software and Compiler Optimizations (554).mp4	12.4 MB
/Video Lecture/L15- Multithreading/
15 - 1 - L15S1 Reduction Scatter_Gather and the Cray 1 (920).mp4	24.6 MB
15 - 2 - L15S2 SIMD (658).mp4	16.2 MB
15 - 3 - L15S3 GPUs (2002).mp4	47.4 MB
15 - 4 - L15S4 Multithreading Motivation (733).mp4	17.0 MB
15 - 5 - L15S5 Course-Grain Multithreading (2616).mp4	62.8 MB
15 - 6 - L15S6 Simultaneous Multithreading (1253).mp4	31.9 MB
/.../L16- Parallel Programming 1/
16 - 1 - L16S1 SMT Implementation (1719).mp4	34.6 MB
16 - 2 - L16S2 Introduction to Parallelism (1759).mp4	37.0 MB
16 - 3 - L16S3 Sequential Consistency (2100).mp4	42.5 MB
16 - 4 - L16S4 Introduction to Locks (0339).mp4	7.7 MB
/.../L17- Parallel Programming 2/
17 - 1 - L17S1 Sequential Consistency Review (348).mp4	8.9 MB
17 - 2 - L17S2 Locks and Semaphores (1001).mp4	19.8 MB
17 - 3 - L17S3 Atomic Operations (2711).mp4	53.8 MB
17 - 4 - L17S4 Memory Fences (1111).mp4	23.8 MB
17 - 5 - L17S5 Dekkers Algorithm (1413).mp4	30.0 MB
/.../L18- Small Multi Processors/
18 - 1 - L18S1 Locking Review (156).mp4	4.5 MB
18 - 2 - L18S2 Bus Implementation (1012).mp4	19.4 MB
18 - 3 - L18S3 Cache Coherence (1225).mp4	22.0 MB
18 - 4 - L18S4 Bus-Based Multiprocessors (1209).mp4	24.9 MB
18 - 5 - L18S5 Cache Coherence Protocols (3322).mp4	67.2 MB
/.../L19- Multiprocessor Interconnect 1/
19 - 1 - L19S1 More Cache Coherence Protocols (2116).mp4	43.9 MB
19 - 2 - L19S2 Introduction to Interconnection Networks (829).mp4	15.8 MB
19 - 3 - L19S3 Message Passing (2659).mp4	51.0 MB
19 - 4 - L19S4 Interconnect Design (1506).mp4	30.4 MB
/.../L2 - Pipelining Review/
2 - 1 - L2S1 Microcoded Microarchitecture (1408).mp4	39.6 MB
2 - 2 - L2S2 Pipeline Basics (3051).mp4	67.8 MB
2 - 3 - L2S3 Structural Hazard (1013).mp4	24.3 MB
2 - 4 - L2S4 Data Hazards (4633).mp4	97.4 MB
/.../L20- Multiprocessor Interconnect 2/
20 - 1 - L20S1 Networking Review (756).mp4	19.9 MB
20 - 2 - L20S2 Topology (1853).mp4	41.9 MB
20 - 3 - L20S3 Topology Parameters (1425).mp4	35.4 MB
20 - 4 - L20S4 Network Performance (1535).mp4	33.3 MB
20 - 5 - L20S5 Routing and Flow Control (2027).mp4	50.3 MB
/.../L21- Large Multiprocessors/
21 - 1 - L21S1 Credit Based Flow Control (723).mp4	14.8 MB
21 - 2 - L21S2 Deadlock (1009).mp4	19.8 MB
21 - 3 - L21S3 False Sharing (929).mp4	15.6 MB
21 - 4 - L21S4 Introduction to Directory Coherence (1255).mp4	23.6 MB
21 - 5 - L21S5 Implementation (2902).mp4	59.8 MB
21 - 6 - L21S6 Scalability of Directory Coherence (1331).mp4	25.0 MB
/.../L3 - Cache Review/
3 - 1 - L3S1 Control Hazards Jumps (1556).mp4	28.3 MB
3 - 2 - L3S2 Control Hazards Branch (2402).mp4	49.8 MB
3 - 3 - L3S3 Control Hazards Others(751).mp4	16.4 MB
3 - 4 - L3S4 Memory Technologies (2247).mp4	52.9 MB
3 - 5 - L3S5 Motivation for Caches (2225).mp4	46.2 MB
/Video Lecture/L4 - Superscalar 1/
4 - 1 - L4S1 Classifying Caches (2807).mp4	59.6 MB
4 - 2 - L4S2 Cache Performance (1711).mp4	32.8 MB
4 - 3 - L4S3 Superscalar 1 (642).mp4	14.1 MB
4 - 4 - L4S4 Basic Two-way In-order Superscalar (456).mp4	9.9 MB
4 - 5 - L4S5 Fetch Logic and Alignment (1101).mp4	20.0 MB
/.../L5 - Superscalar 2 & Exceptions/
5 - 1 - L5S1 Baseline Superscalar and Alignment (416).mp4	8.9 MB
5 - 2 - L5S2 Interrupts and Bypassing (1213).mp4	24.8 MB
5 - 3 - L5S3 Interrupts and Exceptions (2925).mp4	60.0 MB
5 - 4 - L5S4 Introduction to Out-of-Order Processors (3053).mp4	64.9 MB
/Video Lecture/L6 - Superscalar 3/
6 - 1 - L6S1 Review of Out-of-Order Processors (326).mp4	7.2 MB
6 - 2 - L6S2 I2O2 Processors (1958).mp4	40.7 MB
6 - 3 - L6S3 I2O1 Processors (2844).mp4	57.5 MB
6 - 4 - L6S4 IO3 Processors (1623).mp4	33.6 MB
6 - 5 - L6S5 IO2I Processors (431).mp4	8.5 MB
/Video Lecture/L7 - Superscalar 4/
7 - 1 - L7S1 Speculation and Branch (1437).mp4	30.5 MB
7 - 2 - L7S2 Register Renaming Introduction (1108).mp4	23.2 MB
7 - 3 - L7S3 Register Renaming with Pointers to IQ and ROB (2454).mp4	53.0 MB
7 - 4 - L7S4 Register Renaming with Values in IQ and ROB (1214).mp4	25.7 MB
7 - 5 - L7S5 Memory Disambiguation (949).mp4	19.3 MB
/Video Lecture/L8 - VLIW 1/
8 - 1 - L8S1 Limits of Out-of-Order Design Complexity (1313).mp4	26.9 MB
8 - 2 - L8S2 Introduction to VLIW (2157).mp4	44.3 MB
8 - 3 - L8S3 VLIW Compiler Optimizations (2120).mp4	42.0 MB
8 - 4 - L8S4 Classic VLIW Challenges (818).mp4	16.3 MB
8 - 5 - L8S5 Introduction to Predication (951).mp4	20.2 MB
/Video Lecture/L9 - VLIW 2/
9 - 1 - L9S1 Scheduling Model Review (558).mp4	21.0 MB
9 - 2 - L9S2 Review of Predication (3048).mp4	76.8 MB
9 - 3 - L9S3 Predication Implementation (1006).mp4	25.0 MB
9 - 4 - L9S4 Speculation Execution (2602).mp4	51.5 MB
9 - 5 - L9S5 Dynamic Events and Clustered VLIWs (1042).mp4	24.3 MB
9 - 6 - L9S6 Case Study IA-64_Itanium (2110).mp4	51.5 MB
Total files 108