CourseLala com Udemy Verilog HDL Fundamentals for Digital Design and Verification

CourseLala com Udemy Verilog HDL Fundamentals for Digital Design and Verification

Name	[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification	DOWNLOAD Copy Link
Total Size	3.6 GB
Total Files	421
Last Seen	2024-11-17 00:37
Hash	EF43BFD5447F98911C3F45EF02D438E92F6C4B04

/
Get Bonus Downloads Here.url	0.2 KB
/1. Introduction/
1. Welcome!.mp4	45.8 MB
1. Welcome!.srt	4.5 KB
2. Course overview.mp4	52.9 MB
2. Course overview.srt	5.0 KB
3. What is Verilog HDL.mp4	18.1 MB
3. What is Verilog HDL.srt	1.6 KB
4. Understand Abstraction Levels.mp4	32.1 MB
4. Understand Abstraction Levels.srt	3.3 KB
5. Discover the Modern Digital Design Flow.mp4	22.2 MB
5. Discover the Modern Digital Design Flow.srt	3.2 KB
/.../10. Verilog Memory Design/
1. Basics of Semiconductor Memory.mp4	28.1 MB
1. Basics of Semiconductor Memory.srt	2.6 KB
2. Action Time - Single Port Async Read SRAM.mp4	53.5 MB
2. Action Time - Single Port Async Read SRAM.srt	6.6 KB
2.1 ram_sp_async_read.v	3.5 KB
3. Action Time - Single Port Sync Read SRAM.mp4	26.0 MB
3. Action Time - Single Port Sync Read SRAM.srt	3.2 KB
3.1 ram_sp_sync_read.v	3.5 KB
4. Action Time - Dual Port Async Read SRAM.mp4	52.3 MB
4. Action Time - Dual Port Async Read SRAM.srt	6.7 KB
4.1 ram_dp_async_read.v	4.5 KB
5. Action Time - Single Port Sync Read ROM.mp4	39.5 MB
5. Action Time - Single Port Sync Read ROM.srt	4.9 KB
5.1 rom_init.hex	0.1 KB
5.2 rom.v	1.6 KB
/.../11. Verilog State Machines/
1. Discover Finite State Machines.mp4	35.6 MB
1. Discover Finite State Machines.srt	4.3 KB
2. Action Time - Metro turnstile (Mealy FSM).mp4	73.4 MB
2. Action Time - Metro turnstile (Mealy FSM).srt	10.2 KB
2.1 fsm.v	3.1 KB
3. Action Time - Special Semaphore (Mealy FSM).mp4	108.0 MB
3. Action Time - Special Semaphore (Mealy FSM).srt	14.0 KB
3.1 semaphore_fsm.v	3.8 KB
4. Basics of Sequence Detectors.mp4	11.0 MB
4. Basics of Sequence Detectors.srt	1.1 KB
5. Action Time - Sequence Detector NON Overlaping.mp4	32.4 MB
5. Action Time - Sequence Detector NON Overlaping.srt	4.1 KB
5.1 seq_det_non_overlap.v	2.4 KB
6. Action Time - Sequence Detector Overlaping.mp4	12.5 MB
6. Action Time - Sequence Detector Overlaping.srt	1.6 KB
6.1 seq_det_overlap.v	2.4 KB
7. Verilog Mealy FSM Template.mp4	29.5 MB
7. Verilog Mealy FSM Template.srt	3.4 KB
7.1 fsm_template.v	0.9 KB
/.../12. Verilog Design Examples/
1. Discover the First In First Out (FIFO) circuit.mp4	23.9 MB
1. Discover the First In First Out (FIFO) circuit.srt	2.4 KB
2. Action Time - Synchronous FIFO.mp4	81.8 MB
2. Action Time - Synchronous FIFO.srt	10.7 KB
2.1 fifo_sync.v	3.6 KB
3. Action Time - Data Transfer FSM.mp4	114.0 MB
3. Action Time - Data Transfer FSM.srt	14.4 KB
3.1 ram_dp_async_read.v	0.6 KB
3.2 tb_top_fsm.v	3.1 KB
3.3 top_fsm.v	3.7 KB
4. Basics of Data Ecryption.mp4	26.9 MB
4. Basics of Data Ecryption.srt	3.3 KB
5. Action Time - Design a Stream Cypher.mp4	118.4 MB
5. Action Time - Design a Stream Cypher.srt	14.9 KB
5.1 prng.v	0.6 KB
5.2 secret_message.txt	0.1 KB
5.3 tb_encrypt.v	4.4 KB
5.4 top_encrypt_golden.v	1.2 KB
5.5 top_encrypt.v	1.0 KB
6. Congratulations!.mp4	17.3 MB
6. Congratulations!.srt	1.1 KB
/.../2. Install the Simulator/
1. Discover the Verilog Simulation.mp4	18.4 MB
1. Discover the Verilog Simulation.srt	1.5 KB
2. Install Intel Quartus Prime Lite and Modelsim.mp4	20.9 MB
2. Install Intel Quartus Prime Lite and Modelsim.srt	1.9 KB
3. Action Time - Hello World using Verilog.mp4	19.4 MB
3. Action Time - Hello World using Verilog.srt	3.7 KB
3.1 hello_world.v	0.2 KB
4. Congratulations!.mp4	11.4 MB
4. Congratulations!.srt	1.2 KB
/.../3. Verilog Data Types and Operators/
1. Verilog Data types overview.mp4	16.1 MB
1. Verilog Data types overview.srt	1.5 KB
10. Action Time - Bit-wise operators.mp4	14.3 MB
10. Action Time - Bit-wise operators.srt	2.0 KB
10.1 bitwise_operators.v	1.2 KB
11. Verilog Operators - Reduction.mp4	4.6 MB
11. Verilog Operators - Reduction.srt	0.8 KB
12. Action Time - Reduction operators.mp4	14.8 MB
12. Action Time - Reduction operators.srt	1.7 KB
12.1 reduction_operators.v	1.1 KB
13. Verilog Operators - Logical.mp4	8.2 MB
13. Verilog Operators - Logical.srt	0.9 KB
14. Action Time - Logical Operators.mp4	10.6 MB
14. Action Time - Logical Operators.srt	1.3 KB
14.1 logical_operators.v	1.2 KB
15. Action Time - Logical Operators usage.mp4	15.8 MB
15. Action Time - Logical Operators usage.srt	1.8 KB
15.1 logical_operators_usage.v	1.8 KB
16. Verilog Operators - Arithmetic.mp4	3.8 MB
16. Verilog Operators - Arithmetic.srt	0.4 KB
17. Action Time - Arithmetic Operators.mp4	7.9 MB
17. Action Time - Arithmetic Operators.srt	0.9 KB
17.1 math_operators.v	1.3 KB
18. Verilog Operators - Shift.mp4	12.2 MB
18. Verilog Operators - Shift.srt	1.1 KB
19. Action Time - Shift Operators.mp4	12.1 MB
19. Action Time - Shift Operators.srt	1.5 KB
19.1 shift_operators.v	0.8 KB
2. Action time - sum and product.mp4	15.7 MB
2. Action time - sum and product.srt	2.4 KB
2.1 sum_product.v	0.4 KB
20. Verilog Operators - Relational.mp4	6.6 MB
20. Verilog Operators - Relational.srt	0.6 KB
21. Action Time - Relational Operators.mp4	11.0 MB
21. Action Time - Relational Operators.srt	1.4 KB
21.1 relational_operators.v	0.5 KB
22. Verilog Operators - Equality.mp4	10.5 MB
22. Verilog Operators - Equality.srt	1.2 KB
23. Action Time - Equality Operators.mp4	7.3 MB
23. Action Time - Equality Operators.srt	0.8 KB
23.1 equality_operators.v	1.2 KB
24. Verilog Operators - Conditional.mp4	7.0 MB
24. Verilog Operators - Conditional.srt	0.7 KB
25. Action Time - Conditional Operator.mp4	12.9 MB
25. Action Time - Conditional Operator.srt	1.3 KB
25.1 conditional_operators.v	0.6 KB
26. Verilog Operators - Concatenation.mp4	6.7 MB
26. Verilog Operators - Concatenation.srt	0.7 KB
27. Action Time - Concatenation Operator.mp4	14.5 MB
27. Action Time - Concatenation Operator.srt	1.7 KB
27.1 concatention_operator.v	1.0 KB
28. Verilog Operators - Replication.mp4	9.9 MB
28. Verilog Operators - Replication.srt	1.0 KB
29. Action Time - Replication Operator.mp4	17.5 MB
29. Action Time - Replication Operator.srt	1.8 KB
29.1 replication_operator.v	0.8 KB
3. Hardware Description Language data types.mp4	16.5 MB
3. Hardware Description Language data types.srt	1.6 KB
30. Verilog Operators - Precedence.mp4	5.1 MB
30. Verilog Operators - Precedence.srt	0.7 KB
31. Action Time - Operators Precedence.mp4	13.2 MB
31. Action Time - Operators Precedence.srt	1.5 KB
31.1 operators_precedence.v	1.3 KB
32. Congratulations!.mp4	6.7 MB
32. Congratulations!.srt	0.7 KB
4. Action time - Multiple procedures.mp4	18.0 MB
4. Action time - Multiple procedures.srt	2.4 KB
4.1 easy_verilog_example.v	11.1 KB
5. What are Literal Values.mp4	12.9 MB
5. What are Literal Values.srt	1.2 KB
6. Action time - Literal values.mp4	20.3 MB
6. Action time - Literal values.srt	2.1 KB
6.1 literal_values.v	0.9 KB
7. Vectors in Verilog.mp4	11.0 MB
7. Vectors in Verilog.srt	1.0 KB
8. Action time - Vectors.mp4	23.6 MB
8. Action time - Vectors.srt	2.6 KB
8.1 easy_vectors_example.v	1.1 KB
9. Verilog Operators - Bit-wise.mp4	12.6 MB
9. Verilog Operators - Bit-wise.srt	1.6 KB
/4. Verilog Module/
1. Verilog Module - the basics.mp4	36.6 MB
1. Verilog Module - the basics.srt	4.1 KB
2. Action time - Do your first testbench.mp4	30.6 MB
2. Action time - Do your first testbench.srt	4.3 KB
2.1 adder8bit.v	0.1 KB
2.2 my_first_testbench.v	0.8 KB
3. Remember!.mp4	8.0 MB
3. Remember!.srt	0.7 KB
4. What is a Testbench Architecture.mp4	9.7 MB
4. What is a Testbench Architecture.srt	1.3 KB
5. Discover Time and Waveforms.mp4	10.7 MB
5. Discover Time and Waveforms.srt	1.3 KB
6. Action Time - Generate Waveforms.mp4	16.9 MB
6. Action Time - Generate Waveforms.srt	1.8 KB
6.1 waveforms.v	0.4 KB
/.../5. Verilog Design Styles/
1. What are HDL Design Styles.mp4	14.2 MB
1. What are HDL Design Styles.srt	1.2 KB
10. Design a 1bit full_adder.mp4	15.3 MB
10. Design a 1bit full_adder.srt	1.6 KB
11. Action Time - full_adder structural.mp4	18.8 MB
11. Action Time - full_adder structural.srt	2.5 KB
11.1 full_adder_structural.v	1.8 KB
12. Action Time - full_adder dataflow.mp4	11.7 MB
12. Action Time - full_adder dataflow.srt	1.6 KB
12.1 full_adder_dataflow.v	1.4 KB
13. Action Time - full_adder behavioral.mp4	19.6 MB
13. Action Time - full_adder behavioral.srt	2.2 KB
14. Design a 4bit full_adder.mp4	10.0 MB
14. Design a 4bit full_adder.srt	1.2 KB
15. Action Time - 4bit_full_adder structural.mp4	35.7 MB
15. Action Time - 4bit_full_adder structural.srt	3.9 KB
15.1 ripple_adder_4bit_structural.v	3.0 KB
16. Action Time - 4bit_full_adder dataflow.mp4	18.1 MB
16. Action Time - 4bit_full_adder dataflow.srt	2.3 KB
16.1 ripple_adder_4bit_dataflow.v	2.6 KB
17. Action Time - 4bit_full_adder behavioral.mp4	12.0 MB
17. Action Time - 4bit_full_adder behavioral.srt	1.5 KB
17.1 adder_4bit_behavioral.v	1.2 KB
18. Congratulations!.mp4	9.0 MB
18. Congratulations!.srt	0.9 KB
2. Verilog Structural Design.mp4	10.7 MB
2. Verilog Structural Design.srt	1.3 KB
3. Action Time - half adder structural.mp4	23.6 MB
3. Action Time - half adder structural.srt	3.8 KB
3.1 half_adder_structural.v	0.9 KB
4. Verilog Dataflow style.mp4	7.6 MB
4. Verilog Dataflow style.srt	0.8 KB
5. Action Time - half_adder dataflow.mp4	19.2 MB
5. Action Time - half_adder dataflow.srt	2.6 KB
5.1 half_adder_dataflow.v	0.9 KB
6. Verilog_Behavioral_style.mp4	38.0 MB
6. Verilog_Behavioral_style.srt	3.9 KB
7. Remember!.mp4	7.2 MB
7. Remember!.srt	0.6 KB
8. Action Time - Initial Procedures.mp4	15.1 MB
8. Action Time - Initial Procedures.srt	1.7 KB
8.1 procedures.v	1.1 KB
9. Action Time - half_adder behavioral.mp4	13.8 MB
9. Action Time - half_adder behavioral.srt	1.6 KB
9.1 half_adder_behavioral.v	0.9 KB
/.../6. Verilog Structural Design/
1. What is Structural Design.mp4	9.7 MB
1. What is Structural Design.srt	1.0 KB
10. How to implement a multiplexer using tri-state buffers.mp4	9.9 MB
10. How to implement a multiplexer using tri-state buffers.srt	1.2 KB
11. Action Time - mux_tri-state.mp4	15.8 MB
11. Action Time - mux_tri-state.srt	2.5 KB
11.1 mux_tristate.v	0.8 KB
12. Discover the 1bit Comparator.mp4	6.3 MB
12. Discover the 1bit Comparator.srt	0.8 KB
13. Action Time - 1bit_comparator.mp4	21.7 MB
13. Action Time - 1bit_comparator.srt	3.0 KB
13.1 comparator_1bit.v	0.9 KB
14. Remember!.mp4	8.5 MB
14. Remember!.srt	0.7 KB
2. Verilog Built-in_Primitives.mp4	19.9 MB
2. Verilog Built-in_Primitives.srt	2.1 KB
3. Action Time - Built-in_gates.mp4	10.2 MB
3. Action Time - Built-in_gates.srt	1.3 KB
3.1 built_in_gates.v	0.7 KB
3.2 tb_gates.v	0.7 KB
4. Discover the Multiplexer.mp4	23.5 MB
4. Discover the Multiplexer.srt	2.5 KB
5. Action Time - 1bit_mux.mp4	17.4 MB
5. Action Time - 1bit_mux.srt	2.7 KB
5.1 mux_1bit.v	0.3 KB
5.2 tb_mux.v	0.5 KB
6. Discover the Demultiplexer.mp4	16.2 MB
6. Discover the Demultiplexer.srt	2.0 KB
7. Action Time -1bit_demux.mp4	19.9 MB
7. Action Time -1bit_demux.srt	2.6 KB
7.1 demux_1bit.v	0.2 KB
7.2 tb_demux.v	0.6 KB
8. The Tri-state buffer.mp4	8.8 MB
8. The Tri-state buffer.srt	1.1 KB
9. Action Time - tri-state_buffer.mp4	11.0 MB
9. Action Time - tri-state_buffer.srt	1.7 KB
9.1 tb_tristate.v	0.5 KB
9.2 tristate_buffer_1bit.v	0.1 KB
/.../7. Verilog Combinational Design/
1. What is Combinational logic.mp4	20.4 MB
1. What is Combinational logic.srt	2.0 KB
10. Differentiate between binary encoders and decoders.mp4	16.2 MB
10. Differentiate between binary encoders and decoders.srt	1.7 KB
11. Action Time - Nbit Decoder.mp4	23.6 MB
11. Action Time - Nbit Decoder.srt	3.1 KB
11.1 decoder_nbit.v	1.0 KB
12. How to use multiple binary decoders.mp4	9.7 MB
12. How to use multiple binary decoders.srt	1.1 KB
13. Action Time - 4to16 binary Decoder.mp4	30.1 MB
13. Action Time - 4to16 binary Decoder.srt	4.1 KB
13.1 decoder_4to16.v	1.8 KB
14. Action Time - 8to3 Encoder.mp4	24.5 MB
14. Action Time - 8to3 Encoder.srt	3.5 KB
14.1 encoder_8to3.v	11.7 KB
15. What is a Priority Encoder.mp4	17.5 MB
15. What is a Priority Encoder.srt	1.9 KB
16. Action Time - Priority Encoder1 4to2.mp4	18.8 MB
16. Action Time - Priority Encoder1 4to2.srt	2.5 KB
16.1 prio_enc1_4to2.v	1.2 KB
17. Action Time - Priority Encoder2 4to2.mp4	18.8 MB
17. Action Time - Priority Encoder2 4to2.srt	2.2 KB
17.1 prio_enc2_4to2.v	11.3 KB
18. Discover bus Multiplexers.mp4	12.6 MB
18. Discover bus Multiplexers.srt	1.5 KB
19. Action Time - mux_4x_nbit.mp4	23.8 MB
19. Action Time - mux_4x_nbit.srt	2.9 KB
19.1 mux_4x_nbit.v	1.4 KB
2. Discover Continuous assignments.mp4	11.2 MB
2. Discover Continuous assignments.srt	1.1 KB
20. Discover bus Demultiplexers.mp4	9.1 MB
20. Discover bus Demultiplexers.srt	1.3 KB
21. Action Time - demux_4x_nbit.mp4	30.5 MB
21. Action Time - demux_4x_nbit.srt	3.5 KB
21.1 demux_nbit_x4.v	1.4 KB
22. Master the Seven Segment Display Decoder.mp4	26.6 MB
22. Master the Seven Segment Display Decoder.srt	2.7 KB
23. Action Time - HEX 7segment decoder.mp4	33.8 MB
23. Action Time - HEX 7segment decoder.srt	3.2 KB
23.1 hex_7seg_decoder.v	1.7 KB
24. How to use digital logic for arithmetic operations.mp4	21.2 MB
24. How to use digital logic for arithmetic operations.srt	2.5 KB
25. Action time - Design an Arithmetical Logical Unit (ALU).mp4	53.3 MB
25. Action time - Design an Arithmetical Logical Unit (ALU).srt	6.8 KB
25.1 ALU.v	3.4 KB
26. Remember!.mp4	7.6 MB
26. Remember!.srt	0.6 KB
3. Action Time - Continuous assignments.mp4	15.1 MB
3. Action Time - Continuous assignments.srt	2.2 KB
3.1 some_logic.v	0.8 KB
4. Action Time - Adder Tree.mp4	20.7 MB
4. Action Time - Adder Tree.srt	2.8 KB
4.1 adders3.v	1.1 KB
5. Discover Procedural Assignments.mp4	20.1 MB
5. Discover Procedural Assignments.srt	1.8 KB
6. Action Time - Tree Adder Procedural.mp4	17.1 MB
6. Action Time - Tree Adder Procedural.srt	2.3 KB
6.1 adders3_procedural.v	1.5 KB
7. Discover the Nbit Adder.mp4	7.6 MB
7. Discover the Nbit Adder.srt	0.8 KB
8. Action Time - Nbit Adder.mp4	23.3 MB
8. Action Time - Nbit Adder.srt	3.3 KB
8.1 adder_nbit.v	1.0 KB
9. Action Time - Nbit Comparator.mp4	23.7 MB
9. Action Time - Nbit Comparator.srt	3.1 KB
9.1 comparator_nbit.v	1.3 KB
/.../8. Verilog Sequential Design/
1. Sequential Logic Basics.mp4	26.7 MB
1. Sequential Logic Basics.srt	2.8 KB
10. Discover the Shift Register.mp4	23.5 MB
10. Discover the Shift Register.srt	2.4 KB
11. Action Time - Shift_Reg_PIPO.mp4	27.1 MB
11. Action Time - Shift_Reg_PIPO.srt	3.6 KB
11.1 shift_reg_pipo.v	11.5 KB
12. Action Time - Shift_Reg_SIPO.mp4	35.2 MB
12. Action Time - Shift_Reg_SIPO.srt	4.3 KB
12.1 shift_reg_sipo.v	1.5 KB
13. Action Time - Shift_Reg_SISO.mp4	21.3 MB
13. Action Time - Shift_Reg_SISO.srt	2.7 KB
13.1 shift_reg_siso.v	1.4 KB
14. Action Time - Shift_Reg_PISO.mp4	41.9 MB
14. Action Time - Shift_Reg_PISO.srt	6.0 KB
14.1 shift_reg_piso.v	1.6 KB
15. Action Time - Shift_Left_Right_Reg.mp4	40.5 MB
15. Action Time - Shift_Left_Right_Reg.srt	5.3 KB
15.1 shift_left_right_load_reg.v	2.1 KB
16. Discover the Linear Feedback Shift Register.mp4	16.2 MB
16. Discover the Linear Feedback Shift Register.srt	1.8 KB
17. Action Time - Linear Feedback Shift Register.mp4	40.9 MB
17. Action Time - Linear Feedback Shift Register.srt	5.3 KB
17.1 lfsr_16.v	1.3 KB
18. Discover Synchronous Counters.mp4	20.9 MB
18. Discover Synchronous Counters.srt	2.3 KB
19. Action Time - Nbit Counter.mp4	24.6 MB
19. Action Time - Nbit Counter.srt	3.3 KB
19.1 counter_nbit.v	1.2 KB
2. Action Time - Clocks Generator.mp4	30.6 MB
2. Action Time - Clocks Generator.srt	4.0 KB
2.1 clkgen.v	0.9 KB
20. Action Time - Nbit updown Counter.mp4	39.1 MB
20. Action Time - Nbit updown Counter.srt	4.9 KB
20.1 counter_up_down_load_nbit.v	2.1 KB
21. Action Time - Modulo_N Counter.mp4	33.7 MB
21. Action Time - Modulo_N Counter.srt	4.2 KB
21.1 counter_modulo_n.v	1.5 KB
22. Discover Digital Frequency Dividers.mp4	20.4 MB
22. Discover Digital Frequency Dividers.srt	2.1 KB
23. Action Time - Clock Divider Nbit.mp4	23.8 MB
23. Action Time - Clock Divider Nbit.srt	3.3 KB
23.1 clock_div_nbit.v	1.8 KB
24. Action Time - Clock Divider by 3.mp4	38.5 MB
24. Action Time - Clock Divider by 3.srt	4.8 KB
24.1 clock_div_3.v	2.0 KB
3. Types of Sequential Digital Logic.mp4	20.0 MB
3. Types of Sequential Digital Logic.srt	2.2 KB
4. Action Time - The D_Latch.mp4	18.3 MB
4. Action Time - The D_Latch.srt	2.4 KB
4.1 d_latch.v	1.1 KB
5. Action Time - D_Latch_reset_n.mp4	17.3 MB
5. Action Time - D_Latch_reset_n.srt	2.4 KB
5.1 d_latch_rstn.v	1.2 KB
6. Basics of edge-triggered logic.mp4	29.3 MB
6. Basics of edge-triggered logic.srt	3.4 KB
7. Action Time - D_Flip_Flop_sync_rstn.mp4	44.1 MB
7. Action Time - D_Flip_Flop_sync_rstn.srt	5.9 KB
7.1 d_ff_sync_rstn.v	1.3 KB
8. Action Time - D_Flip_Flop_async_rstn.mp4	16.3 MB
8. Action Time - D_Flip_Flop_async_rstn.srt	1.9 KB
8.1 d_ff_async_rstn.v	1.4 KB
9. Remember!.mp4	12.0 MB
9. Remember!.srt	1.1 KB
/.../9. Verilog Functions and Tasks/
1. Verilog Functions Basics.mp4	22.5 MB
1. Verilog Functions Basics.srt	2.2 KB
10. Action Time - Verilog Tasks Control Shift Reg.mp4	20.0 MB
10. Action Time - Verilog Tasks Control Shift Reg.srt	2.5 KB
10.1 task_control_shift_reg.v	1.9 KB
11. Why our code looks like software.mp4	15.0 MB
11. Why our code looks like software.srt	1.4 KB
12. Action Time - Shift Reg PIPO buggy.mp4	41.7 MB
12. Action Time - Shift Reg PIPO buggy.srt	5.2 KB
12.1 shift_reg_pipo_buggy.v	2.5 KB
13. Discover Automated Verification.mp4	20.8 MB
13. Discover Automated Verification.srt	2.5 KB
14. Action Time - ALU self-checking testbench.mp4	62.3 MB
14. Action Time - ALU self-checking testbench.srt	6.9 KB
14.1 ALU.v	7.2 KB
2. Action Time - Verilog Functions1.mp4	13.2 MB
2. Action Time - Verilog Functions1.srt	1.8 KB
2.1 function_ex1.v	0.6 KB
3. Action Time - Verilog Functions2.mp4	10.7 MB
3. Action Time - Verilog Functions2.srt	1.3 KB
3.1 function_ex2.v	0.6 KB
4. Discover Verilog Recursive Functions.mp4	16.0 MB
4. Discover Verilog Recursive Functions.srt	1.6 KB
5. Action Time - Verilog Functions Factorial.mp4	16.5 MB
5. Action Time - Verilog Functions Factorial.srt	2.2 KB
5.1 function_ex3.v	0.6 KB
6. Action Time - Verilog Functions Fibonacci.mp4	12.0 MB
6. Action Time - Verilog Functions Fibonacci.srt	1.4 KB
6.1 function_ex4.v	0.7 KB
7. Action Time - Nbit Comparator Function.mp4	29.6 MB
7. Action Time - Nbit Comparator Function.srt	3.8 KB
7.1 compare_nbit_func.v	1.6 KB
8. Verilog Tasks Basics.mp4	10.4 MB
8. Verilog Tasks Basics.srt	1.1 KB
9. Action Time - Verilog Tasks Distance Conversion.mp4	11.5 MB
9. Action Time - Verilog Tasks Distance Conversion.srt	1.4 KB
9.1 task_meters_to_feet.v	0.8 KB
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Bonus Resources.txt	0.4 KB
Total files 421