DevCourseWeb com Udemy Communication Series P1 Uart Spi And I2C In Verilog

DevCourseWeb com Udemy Communication Series P1 Uart Spi And I2C In Verilog

Name	[ DevCourseWeb.com ] Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog	DOWNLOAD Copy Link Trouble downloading? see How To
Total Size	2.3 GB
Total Files	89
Last Seen	2025-07-18 23:59
Hash	1BA415436FBCC89DF955A0907711D439467810CB

/
Get Bonus Downloads Here.url	0.2 KB
/1 - UART/
1 - Simple UART TX.mp4	84.0 MB
10 - UART 16550 FIFO P4.mp4	9.6 MB
11 - FIFO TB.mp4	31.6 MB
12 - Design Code.html	5.6 KB
13 - Testbench Code.html	0.8 KB
14 - TUART 16550 TX Understanding Oversampling in Baud Generator.mp4	50.1 MB
15 - UART 16550 TX LCR Line Control Register.mp4	94.3 MB
16 - UART 16550 TX Stop bits.mp4	49.2 MB
17 - UART 16550 TX TX Logic.mp4	52.1 MB
18 - UART 16550 TX TX TB.mp4	47.0 MB
19 - Design Code.html	6.8 KB
2 - Simple UART RX.mp4	20.5 MB
20 - TB Code.html	1.1 KB
21 - UART 16550 RX RX Logic.mp4	76.4 MB
22 - UART 16550 RX RX TB.mp4	47.9 MB
23 - Design Code.html	8.4 KB
24 - TB Code.html	1.2 KB
25 - UART 16550 Registers Overview.mp4	28.3 MB
26 - UART 16550 Registers THR and RBR.mp4	92.8 MB
27 - UART 16550 Registers Divisor Latch.mp4	42.0 MB
28 - UART 16550 Registers FCR and LCR.mp4	46.3 MB
29 - UART 16550 Registers LSR.mp4	47.9 MB
3 - Simple UART TB.mp4	43.0 MB
30 - UART 16550 Registers TB.mp4	38.9 MB
31 - Design Code.html	13.4 KB
32 - TB Code.html	1.2 KB
33 - Complete Design.mp4	12.8 MB
34 - TX testbench.mp4	65.9 MB
35 - Design Code.html	34.6 KB
36 - TB Code.html	1.1 KB
4 - Design Code.html	3.7 KB
5 - TB Code.html	0.9 KB
6 - UART 16550A Overview.mp4	16.9 MB
7 - UART 16550 FIFO P1.mp4	10.7 MB
8 - UART 16550 FIFO P2.mp4	42.7 MB
9 - UART 16550 FIFO P3.mp4	16.4 MB
/2 - SPI/
37 - SPI protocol without different mode.mp4	23.8 MB
38 - SPI Master P1.mp4	33.8 MB
39 - SPI Master P2.mp4	40.3 MB
40 - SPI Master P3.mp4	23.6 MB
41 - Code.html	3.7 KB
42 - SPI Slave P1.mp4	10.7 MB
43 - SPI Slave P2.mp4	11.0 MB
44 - Code.html	4.8 KB
45 - Alternate Implementation.mp4	24.7 MB
46 - Code.html	3.2 KB
47 - Understanding CPOL behavior.mp4	79.5 MB
48 - Implementation.mp4	28.0 MB
49 - Code.html	1.8 KB
50 - Understanding CPHA.mp4	37.3 MB
51 - Understanding SPI Modes with different CPOL and CPHA.mp4	17.6 MB
52 - Working with CPHA Master.mp4	28.7 MB
53 - Master TB.mp4	18.7 MB
54 - Code.html	2.9 KB
55 - Working with CPHA Slave.mp4	22.4 MB
56 - Code.html	3.2 KB
57 - Digilent PMOD DA4 Analog Devices AD5628 Understanding Specifications.mp4	66.6 MB
58 - Digilent PMOD DA4 Analog Devices AD5628 Master Design.mp4	24.6 MB
59 - Digilent PMOD DA4 Analog Devices AD5628 TB.mp4	15.7 MB
60 - Design Code.html	3.2 KB
61 - TB Code.html	0.4 KB
62 - Daisy Chain Configuration.mp4	19.1 MB
63 - Master.mp4	20.7 MB
64 - Slave.mp4	11.5 MB
65 - Testbench.mp4	33.0 MB
66 - Design Code.html	5.5 KB
67 - TB Code.html	0.3 KB
68 - One Notes.html	0.8 KB
/3 - I2C/
69 - Overview.mp4	23.3 MB
70 - Understanding I2C Open Drain Interface.mp4	15.9 MB
71 - Start and Stop Conditions.mp4	17.6 MB
72 - I2C Write and Read Transactions.mp4	30.4 MB
73 - I2C Master FSM without Clock Stretch.mp4	13.5 MB
74 - I2C Master without clock stretch.mp4	193.7 MB
75 - Master TB.mp4	38.6 MB
76 - Design Code.html	15.4 KB
77 - TB Code.html	0.5 KB
78 - I2C Slave without clock stretch.mp4	91.9 MB
79 - Testbench for top.mp4	51.7 MB
80 - Design Code.html	29.2 KB
81 - TB Code.html	1.0 KB
82 - Bit Banging.mp4	59.0 MB
83 - Understanding Clock Stretching.mp4	21.1 MB
84 - Implementation of Master.mp4	17.2 MB
85 - Implementation of Slave.mp4	27.6 MB
86 - Design Code.html	31.2 KB
87 - TB Code.html	0.9 KB
/~Get Your Files Here !/
Bonus Resources.txt	0.4 KB
Total files 89