Digital | A2D91A9358F103A3A03A2B5FBAB2EBEFC040FA85

Digital

Name	digital	DOWNLOAD Copy Link
Total Size	10.2 GB
Total Files	225
Hash	A2D91A9358F103A3A03A2B5FBAB2EBEFC040FA85

/4.Sequential Cicuit/
3-DLD SR Flipflop.mp4	160.8 MB
1-DLD Introduction to Sequential Circuits.mp4	29.2 MB
2-DLD Latch and Flipflop.mp4	58.6 MB
4-DLD Clocked Flipflops.mp4	47.8 MB
5-DLD Edge Triggered.mp4	21.6 MB
5-DLD Positive Level Triggered.mp4	29.0 MB
6-DLD JK Flipflop.mp4	67.6 MB
7-T-Flipflop.mp4	27.5 MB
8-DLD D-Flipflop.mp4	48.0 MB
9-DLD Example on Flipflop 1.mp4	54.4 MB
10-DLD Example on Flipflop 2.mp4	42.4 MB
11-DLD Introduction to Flipflop Inter Conversion.mp4	86.5 MB
12-inter conversions of flipflops.mp4	39.9 MB
13-DLD Inter Conversion of Flipflops Example 2.mp4	34.0 MB
13.1-DLD Inter Conversion of Flipflops Example 3.mp4	47.6 MB
14-DLD Inter Conversion of Flipflops Example 4.mp4	13.1 MB
15-DLD Inter Conversion of Flipflops Example 5.mp4	8.9 MB
16-DLD Introduction to Counters.mp4	30.7 MB
17-DLD Asynchronous and Synchronous Counters.mp4	43.3 MB
18-DLD Shift Counters.mp4	44.8 MB
19-DLD Mod 2 Ring Counters.mp4	26.6 MB
20-Mod 4 Ring Counters .mp4	60.1 MB
21-DLD Mod 4 Johnson Counter.mp4	20.4 MB
22-DLD Mod 6 Johnson Counter.mp4	27.8 MB
23-DLD Mod 4 Gray Counter using T-FF.mp4	80.3 MB
24-gray_counter.mp4	25.1 MB
25-Mod 4 Gray Counter using 1 D and 1 T flipflop.mp4	17.8 MB
26-DLD Counter using two different FFs.mp4	69.9 MB
27-DLD Model on analysis Counting States and Sequence Generations.mp4	58.3 MB
28-DLD Deriving the Clock Frequency.mp4	26.6 MB
29-DLD Example on selfstarting and free running Counters.mp4	24.6 MB
29.0-DLD Self starting and free running.mp4	57.9 MB
30-Counter using 3 different FFs.mp4	29.8 MB
31-DLD Example on Combinational Circuits and FFs.mp4	34.9 MB
32-DLD Introduction to Asynchronous Counters.mp4	17.1 MB
33 - Mod 8 up Counter.mp4	120.4 MB
33-Mod 4 up Counter.mp4	20.1 MB
34-DLD Mod 4 down Counter.mp4	9.5 MB
35-DLD Mod 8 random Counter.mp4	31.4 MB
36-DLD Applications of Flip flops.mp4	9.5 MB
37-DLD 3 bit shift right register.mp4	39.0 MB
38-Example 1 on shift right register.mp4	25.3 MB
39-DLD Example 2 on shift right register.mp4	17.6 MB
40-DLD Binary to gray convertor.mp4	25.3 MB
41-DLD Finding 2s complement.mp4	50.0 MB
/
DLD IEEE 754 -- Single and double precision.mp4	88.8 MB
DLD Single precision example 1.mp4	12.5 MB
DLD Single precision example 2.mp4	14.0 MB
NS 10(Introduction to floating point representation).mp4	72.2 MB
NS 12(Floating point representation ex 1).mp4	50.7 MB
NS 14 (Floating point number example 2 - part 2).mp4	27.3 MB
DLD GATE questions -- 4.mp4	65.9 MB
/1.Number System/
1-inttroduction to number system.mp4	45.8 MB
2-DLD Conversion to base 10.mp4	50.8 MB
3-DLD Conversion from base 10.mp4	76.2 MB
4-DLD Minimum number of bits required for inter conversion -- ex 1.mp4	72.6 MB
5-DLD Minimum number of bits required for inter conversion -- ex 2.mp4	38.0 MB
6-DLD Example 3.mp4	27.2 MB
7-DLD Complementary number system.mp4	99.1 MB
8-DLD Why we use complements.mp4	56.4 MB
9-DLD Substraction in diminished radix complement.mp4	66.4 MB
10-DLD Examples on diminished radix complement.mp4	94.9 MB
11-Examples on subtraction in radix complement.mp4	99.3 MB
12-DLD Summary of subtraction using complements incase of unsigned numbers.mp4	48.7 MB
13-DLD Signed number representation.mp4	22.9 MB
14-DLD Example on signed number representations.mp4	86.4 MB
15-DLD Ranges of signed number representations.mp4	74.0 MB
16-Examples on Ranges.mp4	39.9 MB
17-DLD Sign bit extension.mp4	69.4 MB
18-DLD Example on sign bit extension.mp4	12.5 MB
19-DLD Overflow.mp4	92.4 MB
20-DLD Classification of binary codes.mp4	42.6 MB
21-DLD 8421 Excess-3 3321 codes.mp4	79.0 MB
22-Examples on codes.mp4	31.4 MB
23-DLD BCD addition.mp4	43.2 MB
24-Excess-3 addition.mp4	26.0 MB
25-DLD Gray code.mp4	54.6 MB
26-DLD Binary to gray and vice versa.mp4	49.5 MB
27-DLD Error detection.mp4	51.7 MB
28-DLD Error correction.mp4	85.6 MB
29-DLD Hamming code.mp4	84.4 MB
30-DLD Examples on Hamming code.mp4	50.3 MB
DLD Example 4.mp4	24.4 MB
DLD Example 5.mp4	10.6 MB
DLD Example 6.mp4	12.5 MB
DLD Example 7.mp4	34.5 MB
DLD Example 8.mp4	48.8 MB
/2.Combinatiinal Circuit/
1-intrduction to logic design.mp4	54.2 MB
2-AND-OR OR-AND realization.mp4	77.1 MB
3-Minimum No_of NAND gates example.mp4	14.9 MB
4-DLD NOR- NOR example.mp4	26.0 MB
5-DLD Minimum Noof NOR gates Example.mp4	10.6 MB
6-DLD Minimum Noof NOR gates Example2.mp4	9.0 MB
7-DLD EX-OR and EX-NOR implementation with NOR and NAND gates.mp4	39.3 MB
8-DLD Half adder.mp4	16.2 MB
9-DLD Half subtracter.mp4	17.5 MB
10-DLD Comparator.mp4	25.2 MB
11-DLD Introduction to MUX.mp4	67.2 MB
12-DLD Proving MUX is functionally complete.mp4	28.4 MB
13-DLD Implementing functions with MUX example 1.mp4	78.4 MB
14-DLD Implementing functions with MUX example 2.mp4	14.5 MB
15-DLD multiplexer with enable input.mp4	49.2 MB
16-DLD relationship between select lines and inputs of a mux.mp4	28.6 MB
17-DLD cascading multiplexers- ex 1.mp4	17.9 MB
18-cascading multiplexers - ex 2.mp4	10.4 MB
19-DLD cascading multiplexers - ex 3.mp4	18.0 MB
20-DLD Expansion of multiplexers.mp4	124.2 MB
21-DLD Assigning select lines while expanding the MUX.mp4	49.3 MB
22-DLD Introduction to Demultiplexer.mp4	117.3 MB
23-DLD introduction to decoder.mp4	68.9 MB
24-DLD implementing functions with decoder example 1.mp4	18.1 MB
25-DLD implementing functions with decoder example 2.mp4	50.1 MB
26-DLD decoder for function implementation - ex3.mp4	23.4 MB
27-DLD converting one code to other code using decoder.mp4	90.3 MB
28-DLD ROM implementation using decoder.mp4	67.1 MB
29-DLD Implementing Functions using only Decoder.mp4	40.1 MB
30-Implementing Functions using Decoder + Multiplexer Example 1.mp4	53.4 MB
31-DLD Implementing Functions using Decoder Multiplexer Example 2.mp4	64.1 MB
32-DLD Decoder with Enable Input.mp4	56.6 MB
33-DLD Constructing 3x8 Decoder using 1x2 Decoder.mp4	41.4 MB
34-DLD Constructing 4x2 Decoder using 1x2 Decoder.mp4	27.6 MB
35-DLD Constructing 6x64 Decoder using 3x8 Decoder.mp4	40.8 MB
36-DLD Expansion of Decoder in general.mp4	56.7 MB
37-DLD Constructing 7x128 Decoder using 3x8 Decoder.mp4	50.1 MB
38-Expansion of Decoders in another way .mp4	63.6 MB
39-DLD Address Expansion of ROM.mp4	63.9 MB
40-DLD Word Expansion of ROM.mp4	46.3 MB
41-DLD Finding the Address ranges of Devices.mp4	63.9 MB
42-Example on Enabling a Device.mp4	37.3 MB
43-DLD Finding the address ranges of Memory Devices.mp4	37.3 MB
44-Introduction to Encoders .mp4	77.3 MB
45-Priority Encoders .mp4	37.4 MB
46-DLD Introduction to Hazards.mp4	36.9 MB
47-DLD Hazards and test vectors.mp4	33.5 MB
48-DLD Examples on Test Vectors.mp4	43.8 MB
49-DLD Half Adder_+2.mp4	16.9 MB
50-DLD Full Adder.mp4	41.4 MB
51-DLD Ripple Carry Adder.mp4	38.6 MB
52-DLD Carry Lookahead Adder.mp4	64.0 MB
53-DLD Carry look ahead adder implementation.mp4	35.2 MB
54-DLD Hybrid adder.mp4	28.7 MB
55-DLD Serial adder.mp4	31.3 MB
56-DLD Binary addersubtractor.mp4	41.0 MB
57-DLD BCD adder.mp4	47.1 MB
58-DLD Invalid combinations for BCD adder.mp4	18.1 MB
59-DLD 2 bit comparator.mp4	65.9 MB
60-DLD 3 4 bit comparators.mp4	36.0 MB
61-Analysing all the cases of comparators.mp4	4.2 MB
DLD Implementing functions with MUX example 2_.mp4	14.5 MB
f1..png	120.5 KB
f2.png	115.4 KB
f3.png	107.8 KB
f4.png	96.8 KB
/3.Minimization/
1-Intoduction to Minimization of Boolean expressions.mp4	32.4 MB
2-Irredundant (or) Irreducible Expressions.mp4	55.1 MB
3-K-Map Introduction.mp4	84.2 MB
4-K map Simplification.mp4	115.1 MB
5-Examples on K-Map.mp4	68.8 MB
6-DLD Covering Functions.mp4	56.0 MB
7-DLD Implicants and Prime Implicants.mp4	46.1 MB
8-DLD Essential Prime Implicants.mp4	84.4 MB
9-DLD Procedure for obtaining Minimal SOP.mp4	121.6 MB
10-DLD Minimal SOP Example.mp4	44.0 MB
11-DLD Minimal POS.mp4	72.0 MB
12-Examples on Minimal POS.mp4	31.5 MB
13-Introduction to Don't cares.mp4	94.5 MB
14-Examples on don't care set 1.mp4	28.0 MB
15-Examples on don't care set 2.mp4	73.6 MB
16-Examples on don't care set 3.mp4	20.2 MB
17-Finding Minimal Expressions.mp4	44.2 MB
18-Branching Technique for Minimising Cyclic Functions.mp4	58.6 MB
19-Implicant and Prime Implicant Difference.mp4	31.1 MB
20-Converting a Function into Self Dual.mp4	42.4 MB
21-Combining Functions having Don't Cares.mp4	49.1 MB
22-Prime Implicants and Don't Cares.mp4	24.0 MB
23-Number of Minimal Expressions.mp4	10.0 MB
24-Beautiful Question on Prime Implicant Chart .mp4	38.0 MB
25-Variable Entrant Maps(VEM).mp4	29.4 MB
26-Minimisation using VEM.mp4	56.2 MB
27-Example on VEM.mp4	38.1 MB
28-Problem on K-Map.mp4	62.9 MB
29-finding the free variables .mp4	18.7 MB
30-Relationship between Minimal POS SOP in case of don't cares -- 1.mp4	67.1 MB
31-Relationship between Minimal POS SOP in case of don't cares -- 2.mp4	45.7 MB
32-Comparing independent variables in minimal SOP and POS.mp4	27.6 MB
33-Number of irredundant and minimal expressions.mp4	101.3 MB
34-don't cares are never included in the prime Implicant chart.mp4	53.5 MB
35-Number of Irredundant and Minimal Expressions-1.mp4	83.0 MB
36-Functions nvolving Functions Example 1.mp4	61.3 MB
37-Functions involving Functions example 2 .mp4	22.2 MB
38-Functions involving Functions Example 3.mp4	49.2 MB
Expansion of Decoders in another way .mp4	63.6 MB
/loggic-function/
1-Basic properties of switching algebra.mp4	82.4 MB
2-DLD Switching expressions and simplification.mp4	75.1 MB
3-DLD DeMorgans law and simplification.mp4	50.4 MB
4-DLD Switching functions.mp4	44.1 MB
5-DLD Canonical Sum of Products.mp4	44.1 MB
6-DLD Canonical Product of sums.mp4	49.8 MB
7-DLD Examples of canonical forms.mp4	49.7 MB
8-DLD Functional properties.mp4	19.0 MB
9-DLD Number of Functions.mp4	64.0 MB
10-DLD Counting the number of functions and Neutral functions.mp4	47.8 MB
11-DLD Venn diagram representation.mp4	47.8 MB
12-DLD Contact representation.mp4	61.2 MB
13-DLD Nested function.mp4	47.8 MB
14-DLD NAND gate and properties.mp4	28.9 MB
15-DLD NOR gate and Properties.mp4	26.2 MB
16-DLD EX-OR gate and Properties.mp4	60.7 MB
17-DLD EX-NOR gate and Properties.mp4	52.7 MB
17.1-DLD Properties of EX-OR and EX-NOR.mp4	82.3 MB
18-DLD Minimum number of gates required for EX-OR and EX-NOR.mp4	19.1 MB
19.0-DLD Functionally Completeness.mp4	19.1 MB
20-DLD Example 1 on Functional Completeness.mp4	22.1 MB
21-DLD Example 2 on Functional Completeness.mp4	21.7 MB
22-DLD Example 3 on Functional Completeness.mp4	16.3 MB
23-DLD Example 4 on Functional Completeness.mp4	8.0 MB
24-DLD Example 5 on Functional Completeness.mp4	36.9 MB
25-DLD Example 6 on Functional Completeness.mp4	46.5 MB
26-DLD Self Dual Functions.mp4	28.4 MB
27-DLD Number of Self Dual Functions.mp4	43.1 MB
28-Self Dual Functions are closed under Complementation.mp4	29.2 MB
29-Introduction to Electronic gates.mp4	33.4 MB
30-Positive and Negative logic systems.mp4	49.0 MB
Data_Mining__Concepts_and_Techniques__2nd_edition_.pdf	99.8 KB
DataMining_BOOK.pdf	30.1 MB
Total files 225