Getting Started with FPGA Programming with VHDL | 191C5C556BEF0DA85989719225B59CA71FE30844

Getting Started with FPGA Programming with VHDL

Name	Getting Started with FPGA Programming with VHDL	DOWNLOAD Copy Link Trouble downloading? see How To
Total Size	520.8 MB
Total Files	109
Hash	191C5C556BEF0DA85989719225B59CA71FE30844

/05.Writing Sequential Code/
09.Summary.srt	0.6 KB
02.Signals.srt	3.2 KB
04.Wait Statement.srt	3.4 KB
01.Overview.srt	3.6 KB
03.Processes.srt	4.2 KB
06.Variables.srt	5.4 KB
07.If, Case, and Loop Statements.srt	5.5 KB
05.More Data Types.srt	6.0 KB
08.Demo - Sequential Constructs.srt	9.9 KB
09.Summary.mp4	825.3 KB
02.Signals.mp4	3.5 MB
01.Overview.mp4	3.5 MB
04.Wait Statement.mp4	3.7 MB
03.Processes.mp4	5.2 MB
06.Variables.mp4	5.8 MB
07.If, Case, and Loop Statements.mp4	6.9 MB
05.More Data Types.mp4	7.3 MB
08.Demo - Sequential Constructs.mp4	31.5 MB
/04.Introduction to VHDL/
07.Summary.srt	1.0 KB
01.Introduction.srt	1.5 KB
03.Entity and Architecture.srt	3.4 KB
02.VHDL.srt	3.7 KB
05.Bits and Bit Vectors.srt	4.3 KB
04.Ports and Board IO.srt	7.9 KB
06.Interacting with Board IO.srt	8.0 KB
07.Summary.mp4	1.4 MB
01.Introduction.mp4	1.6 MB
05.Bits and Bit Vectors.mp4	4.0 MB
03.Entity and Architecture.mp4	4.1 MB
02.VHDL.mp4	4.5 MB
04.Ports and Board IO.mp4	15.5 MB
06.Interacting with Board IO.mp4	31.9 MB
/07.Packages and Components/
07.Summary.srt	1.1 KB
01.Overview.srt	2.1 KB
05.Generate Statement.srt	3.4 KB
03.Packages and Libraries.srt	4.5 KB
02.The IEEE Library and Standard Logic.srt	5.6 KB
04.Components and Port Maps.srt	5.9 KB
06.Demo - Packages and Components.srt	13.0 KB
07.Summary.mp4	1.9 MB
01.Overview.mp4	2.1 MB
05.Generate Statement.mp4	4.0 MB
03.Packages and Libraries.mp4	5.9 MB
04.Components and Port Maps.mp4	7.3 MB
02.The IEEE Library and Standard Logic.mp4	8.0 MB
06.Demo - Packages and Components.mp4	48.3 MB
/08.Debugging and Analysis/
04.Summary.srt	1.2 KB
01.Overview.srt	1.3 KB
05.Course Summary.srt	2.2 KB
03.SignalTap Logic Analyzer.srt	8.3 KB
02.Simulation with ModelSim.srt	13.7 KB
01.Overview.mp4	1.2 MB
04.Summary.mp4	1.8 MB
05.Course Summary.mp4	3.6 MB
03.SignalTap Logic Analyzer.mp4	19.8 MB
02.Simulation with ModelSim.mp4	43.4 MB
/03.Digital Design Primer/
08.Summary.srt	1.3 KB
01.Overview.srt	1.4 KB
07.Logic Element.srt	1.6 KB
02.Boolean Logic.srt	2.6 KB
06.Clocks and Timing.srt	2.9 KB
05.Flip-flop, MUX, and LUT.srt	4.7 KB
04.Addition and Multiplication.srt	5.8 KB
03.Logic Gates.srt	6.1 KB
01.Overview.mp4	1.4 MB
08.Summary.mp4	2.2 MB
07.Logic Element.mp4	2.3 MB
02.Boolean Logic.mp4	3.6 MB
06.Clocks and Timing.mp4	4.6 MB
03.Logic Gates.mp4	7.0 MB
05.Flip-flop, MUX, and LUT.mp4	7.0 MB
04.Addition and Multiplication.mp4	8.0 MB
/02.FPGA Technology Overview/
02.Module Overview.srt	1.4 KB
09.Summary.srt	1.6 KB
07.Pin Assignments and the Pin Planner.srt	2.7 KB
08.Programming the FPGA.srt	3.3 KB
01.Course Overview.srt	4.3 KB
06.Project Setup.srt	4.5 KB
04.A Look at the Development Board.srt	7.6 KB
05.Setting up the EDA.srt	11.5 KB
03.What Is an FPGA.srt	13.0 KB
02.Module Overview.mp4	1.3 MB
09.Summary.mp4	2.6 MB
01.Course Overview.mp4	4.7 MB
07.Pin Assignments and the Pin Planner.mp4	9.8 MB
08.Programming the FPGA.mp4	10.9 MB
06.Project Setup.mp4	13.2 MB
03.What Is an FPGA.mp4	16.9 MB
05.Setting up the EDA.mp4	20.5 MB
04.A Look at the Development Board.mp4	39.9 MB
/06.Writing Concurrent Code/
06.Clocks.srt	2.1 KB
08.Summary.srt	2.2 KB
02.Delays.srt	3.5 KB
01.Overview.srt	4.0 KB
03.Concurrent Signal Assignments.srt	5.2 KB
04.Conditional Signal Assignments.srt	5.4 KB
05.Block Statement.srt	5.5 KB
07.Demo - Resettable Timer.srt	10.7 KB
08.Summary.mp4	3.0 MB
06.Clocks.mp4	3.1 MB
01.Overview.mp4	3.9 MB
02.Delays.mp4	4.0 MB
03.Concurrent Signal Assignments.mp4	5.8 MB
05.Block Statement.mp4	6.2 MB
04.Conditional Signal Assignments.mp4	6.7 MB
07.Demo - Resettable Timer.mp4	39.2 MB
/01.Course Overview/
01.Course Overview.srt	2.9 KB
01.Course Overview.mp4	9.2 MB
/
fpga-vhdl-programming-getting-started.zip	5.0 MB
Total files 109