Q91 | C669CC82FFD09FE1692319D2D7A7A96B99F75D34

Q91

Name	Q91	DOWNLOAD Copy Link
Total Size	2.2 GB
Total Files	574
Hash	C669CC82FFD09FE1692319D2D7A7A96B99F75D34

/Литература/Aldec Украина/Ch1.files/
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/Литература/Aldec Украина/Ch2.files/
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/Литература/Aldec Украина/Ch3.files/
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/Литература/Aldec Украина/Ch4.files/
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/Литература/Aldec Украина/Ch5.files/
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/Литература/Aldec Украина/Ch6.files/
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/Литература/Aldec Украина/Ch7.files/
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/Литература/Aldec Украина/Ch8.files/
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/Литература/Aldec Украина/Ch9.files/
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/.../Руководство Aldec Украина.files/
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/.../Руководство Aldec Украина2.files/
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/Литература/Aldec Украина/
Ch5.htm	45.8 KB
Ch7.htm	44.0 KB
Ch6.htm	39.0 KB
Ch8.htm	31.1 KB
Руководство Aldec Украина2.htm	25.3 KB
Ch4.htm	25.3 KB
Ch2.htm	24.6 KB
Ch9.htm	23.4 KB
Ch3.htm	22.4 KB
Руководство Aldec Украина.htm	20.5 KB
Ch1.htm	20.0 KB
/.../8x64 Shift Reg/
VHDL 8x64 Shift Register with Taps.mht	95.2 KB
8x64-shift-register-vhd_readme_v1_0.txt	1.8 KB
shift_8x64_taps.zip	0.5 KB
/Литература/Examples Altera/Adder_Sub/
VHDL Adder-Subtractor.mht	93.8 KB
add-sub-vhdl_readme_v1_0.txt	1.9 KB
addsub.zip	0.5 KB
/Литература/Examples Altera/Behavioral Counter/
Feedback.mht	82.5 KB
/Литература/Examples Altera/BIDIR Bus/
Using Tri-State Buses for Bidirectional Communication.mht	130.7 KB
Graphic Editor Tri-State Buses Connected to a Bidirectional Bus.mht	88.8 KB
Graphic Editor Tri-State Buses Converted to a Multiplexer.mht	88.1 KB
Graphic Editor Parameterized Tri-State Bus (CODElpm_bustri-CODE).mht	87.7 KB
VHDL Bidirectional Bus.mht	82.6 KB
tri_bus.gdf	2.6 KB
bid.gdf	2.4 KB
tribus.gdf	1.9 KB
/.../Counter with Sync Load/
VHDL Counter with Synchronous Load.mht	93.7 KB
counter-vhdl_readme_v1_0.txt	1.8 KB
count.zip	0.4 KB
/Литература/Examples Altera/DFFE/
Feedback.mht	81.8 KB
/Литература/Examples Altera/Down Counter/
VHDL Down Counter.mht	86.4 KB
/Литература/Examples Altera/DSP_Func/Signed Multiplier/
VHDL Signed Multiplier.mht	93.3 KB
signed-multiplier-vhdl_readme_v1_0.txt	1.9 KB
signed_mult.zip	0.4 KB
/.../Signed Multiplier_Accumulator/
VHDL Signed Multiply-Accumulator.mht	94.0 KB
sig_altmult_accum.zip	0.5 KB
/.../Unsigned Multiplier with Register IO/
VHDL Unsigned Multiplier with Registered I-O.mht	94.3 KB
unsigned_mult.zip	0.5 KB
/.../Unsigned Multiplier_Adder/
VHDL Unsigned Multiply-Adder.mht	94.5 KB
unsignedmult_add.zip	0.6 KB
/Литература/Examples Altera/DSP_Func/Viterbi/
viterbi_node_sync_design.zip	274.0 KB
VHDL Node Synchronization Design Example for Viterbi Decoder.mht	128.2 KB
/Литература/Examples Altera/LATCH/
VHDL Preventing Unintentional Latch Creation.mht	93.8 KB
prevent-latch-vhdl_readme_v1_0.txt	1.8 KB
nolatch.zip	0.4 KB
/.../Look_ahead Adder/
VHDL Carry Look-Ahead Adder.mht	87.2 KB
/Литература/Examples Altera/LPM_DFFE/
VHDL Instantiating a D Flipflop using lpm_dff.mht	82.0 KB
/.../QDR SRAM Controller/
VHDL QDR SRAM Controller.mht	98.5 KB
/.../Cycle-Shared Dual Port RAM/
Graphic Editor Cycle-Shared Dual-Port RAM (CODEcsdpram-CODE).mht	93.3 KB
VHDL Cycle-Shared Dual-Port RAM (CODEcsdpram-CODE).mht	86.7 KB
cycle.gdf	3.0 KB
/.../Dual Clock Sync RAM/
VHDL Dual Clock Synchronous RAM.mht	95.3 KB
ram_dual.zip	0.5 KB
/.../Single clock Sync RAM with Async Read Address/
VHDL Single Clock Synchronous RAM with Asynhcronous Read Address.mht	91.8 KB
single-clk-syncram-asyncrd-vhdl_readme_v1_0.txt	1.9 KB
single-clk-syncram-asyncrd.zip	0.5 KB
/.../Single clock Sync RAM/
VHDL Single Clock Synchronous RAM.mht	95.3 KB
ram.acf	14.8 KB
single-clock-syncram-vhdl_readme_v1_0.txt	1.8 KB
ram.hif	1.5 KB
ram.vhd	0.9 KB
ram.zip	0.5 KB
/.../Single clock Sync RAM with Async Read Address/
VHDL Single Clock Synchronous RAM with Asynhcronous Read Address.mht	95.7 KB
single-clk-syncram-asyncrd-vhdl_readme_v1_0.txt	1.9 KB
single-clk-syncram-asyncrd.zip	0.5 KB
/.../VHDL Ripple-Carry Adder.files/
style.css	17.6 KB
common.js	8.3 KB
baynote.js	4.8 KB
altera_banner.jpg	4.3 KB
footer_line.jpg	2.1 KB
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njs.gif	0.0 KB
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/.../Ripple_Carry Adder/
VHDL Ripple-Carry Adder.mht	87.3 KB
VHDL Ripple-Carry Adder.htm	31.4 KB
/Литература/Examples Altera/TRI Bus/
VHDLTri-State Buses.mht	81.8 KB
/Литература/Examples Altera/
Using Tri-State Buses for Bidirectional Communication.mht	134.7 KB
VHDL Creating a Hierarchical Design.mht	88.0 KB
VHDL Bidirectional Bus.mht	86.5 KB
VHDLTri-State Buses.mht	85.8 KB
VHDL Converting a Hexadecimal Value to a Standard Logic Vector.mht	85.5 KB
/Литература/IEEE Standard/
std_1076.pdf	11.8 MB
ieee1076_vhdl_2000.pdf	1.5 MB
/Литература/Уэйкерли/
wakerly.djvu	11.7 MB
/Литература/
WinDjView-0.4.2.exe	514.0 KB
/.../Benchmarking and Design Migration Techniques/
an307.pdf	2.6 MB
wp-01047-performing-equivalent-timing-analysis-between-timequest-and-trace.pdf	1.3 MB
an345.pdf	594.7 KB
an311.pdf	292.1 KB
wpfpgapbm.pdf	251.7 KB
wp-01032.pdf	199.4 KB
tb84.pdf	108.7 KB
an307_DesignExample.zip	4.0 KB
/.../Design Guide and Applications/
cookbook.zip	3.8 MB
an567.pdf	2.8 MB
an481.pdf	1.8 MB
stx_cookbook.pdf	1.7 MB
an433.pdf	1.5 MB
an466.pdf	1.3 MB
an370.pdf	1.2 MB
an411.pdf	1.1 MB
emi_debug_timing.pdf	944.3 KB
an469.pdf	643.2 KB
wp-01082-quartus-ii-metastability.pdf	598.1 KB
ug_low_level.pdf	503.9 KB
mnl_timequest_cookbook.pdf	493.4 KB
an428.pdf	435.0 KB
an474.pdf	373.4 KB
Example1.zip	286.1 KB
Example2.zip	238.4 KB
SIII_phase_shift.zip	5.1 KB
/.../Q91 Design Flow/Getting Started/
intro_to_quartus2.pdf	5.1 MB
mnl_qts_quick_start.pdf	549.5 KB
ug_megafunction_overview.pdf	336.9 KB
/.../Installation and Licensing/
quartus_install.pdf	1.6 MB
/.../Other Related Documentation/
an433.pdf	1.5 MB
an370.pdf	1.2 MB
an549.pdf	794.6 KB
an453.pdf	733.3 KB
wp-01044.pdf	712.8 KB
ss-military-vip.pdf	284.8 KB
AN437.pdf	224.3 KB
wp-01062-quartus-ii-increasing-productivity-incremental-compilation.pdf	173.3 KB
/.../Q91 Design Flow/Programming Hardware/
ug_ebcc.pdf	1.2 MB
ug_usb_blstr.pdf	512.1 KB
ug_bbmv.pdf	410.0 KB
ug_bbii.pdf	302.0 KB
ug_mstr_blstr.pdf	227.3 KB
/.../Q91 Design Flow/Release Notes/
rn_qts.pdf	144.9 KB
rn_qts_dev_support.pdf	131.4 KB
/.../Q91 Design Flow/Using Megafunctions/Arithmetic/
Floating-Point DesignExamples_and_ModelSimFiles.zip	37.9 MB
ug_lpm_alt_mfug.pdf	2.0 MB
ug_altfp_mfug.pdf	1.9 MB
altsqrt_DesignExample.zip	202.4 KB
altmemmult_DesignExample.zip	190.6 KB
altmult_complex_DesignExample.zip	160.0 KB
altecc_DesignExample2.zip	118.2 KB
altmult_accum_DesignExample.zip	107.4 KB
parallel_adder_DesignExample.zip	99.5 KB
altaccumulate_DesignExample.zip	91.9 KB
altecc_DesignExample1.zip	81.0 KB
altmult_add_DesignExample.zip	78.8 KB
/.../Q91 Design Flow/Using Megafunctions/DSP/
ug_fft.pdf	1.1 MB
ug_viterbi-compiler.pdf	1.0 MB
ug_nco.pdf	991.4 KB
ug_cic.pdf	798.7 KB
rs-compiler_ug.pdf	657.7 KB
wp-01104-dsp-blockset-sensor.pdf	382.2 KB
/.../Q91 Design Flow/Using Megafunctions/Interfaces/
emi_ddr_ug.pdf	3.4 MB
emi_ddr3_ug.pdf	2.4 MB
ug_ddr_sdram.pdf	1.7 MB
ug_hypertransport.pdf	756.2 KB
ug_asi.pdf	371.9 KB
/.../ALT TEMP SENS/
ug_alttemp_sense.pdf	233.1 KB
alttemp_sense_ex1.zip	11.2 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTASMI PARALLEL/
ug_altasmi_parallel.pdf	404.7 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTCLKCTRL/
ug_altclock.pdf	345.3 KB
altclkctrl_DesignExample.zip	107.0 KB
altclkctrl_msim.zip	4.9 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTDDIO/
ug_altddio.pdf	4.1 MB
altddio_DesignExample_ex2.zip	143.2 KB
altddio_DesignExample_ex1.zip	114.5 KB
altddio_ex1_msim.zip	18.2 KB
altddio_ex2_msim.zip	17.7 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTDLL/
ug_altdll_altdq_dqs.pdf	4.3 MB
altdll_altdq_dqs_DesignExample_ex1.zip	815.1 KB
altdll_altdq_dqs_ex1_msim.zip	406.6 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTDO/
ug_altdq_dqs.pdf	656.9 KB
altdq_dqs_DesignExample.zip	68.5 KB
altdq_dqs_msim.zip	11.6 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTIOBUF/
ug_altiobuf.pdf	1.2 MB
altiobuf_ex1_msim.zip	93.5 KB
altiobuf_design_example_1.zip	57.6 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTLVDS/
ug_altlvds.pdf	989.2 KB
altlvds_ex4_msim.zip	443.4 KB
altlvds_DesignExample_ex3.zip	258.2 KB
altlvds_DesignExample.zip	208.2 KB
altlvds_DesignExample_ex2.zip	115.3 KB
altlvds_ex3_msim.zip	106.7 KB
altlvds_ex1_msim.zip	94.5 KB
altlvds_ex2_msim.zip	59.5 KB
altlvds_DesignExample_ex4.zip	31.7 KB
altlvds_DesignExample_ex5.zip	12.1 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTMEMPHY/
ug_altmemphy.pdf	9.0 MB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTOCT/
ug_altoct.pdf	274.0 KB
altoct_DesignExample.zip	31.8 KB
alt_oct_msim.zip	30.2 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTPLL/
ug_altpll.pdf	825.1 KB
shift_clk.zip	396.1 KB
ddr_clk.zip	100.0 KB
shift_clk_msim.zip	10.7 KB
ddr-clk-msim.zip	6.1 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTPLL RECONFIG/
ug_altpll_reconfig.pdf	7.1 MB
altpll_reconfig_ex3_msim.zip	442.0 KB
altpll_reconfig_DesignExample_ex3.zip	323.6 KB
altpll_reconfig_DesignExample_ex2.zip	193.5 KB
altpll_reconfig_DesignExample_ex1.zip	170.5 KB
altpll_reconfig_ex1_msim.zip	70.0 KB
altpll_reconfig_ex2_msim.zip	69.7 KB
/.../Q91 Design Flow/Using Megafunctions/IO/ALTREMOTE UPDATE/
ug_altremote.pdf	951.1 KB
altremote_update_DesignExample_ex2.zip	16.5 KB
altremote_update_DesignExample_ex1.zip	16.3 KB
altremote_update_ex1_msim.zip	12.5 KB
altremote_update_ex2_msim.zip	12.4 KB
/.../Q91 Design Flow/Using Megafunctions/IO/Flash Memory/
ug_alt_ufm.pdf	1.1 MB
alt_ufm_DesignExample.qar	73.6 KB
alt_ufm_msim.zip	16.4 KB
/.../JTAG-accessible Extensions/AN386/
an386.pdf	2.2 MB
NiosDesign_An386.zip	580.6 KB
flashmem.zip	0.9 KB
/.../JTAG-accessible Extensions/Virtual JTAG/
ug_virtualjtag.pdf	1.3 MB
ug_virtual_jtag_design_example_2.zip	311.0 KB
ug_virtual_jtag_design_example_1.zip	143.8 KB
/.../JTAG-accessible Extensions/
an370.pdf	1.2 MB
/.../Q91 Design Flow/Using Megafunctions/Memory Compiler/ALTMEM INIT/
ug_altmem_init.pdf	536.8 KB
DE2_externalROM.zip	10.0 KB
DE1_internalROM.zip	8.5 KB
/.../Q91 Design Flow/Using Megafunctions/Memory Compiler/ALTOTP/
ug_altotp.pdf	248.4 KB
DesignExample_otpfuse.zip	22.7 KB
/.../Q91 Design Flow/Using Megafunctions/Memory Compiler/ALTSHIFT TAPS/
ug_shift_register_ram_based.pdf	447.4 KB
DE_ALTSHIFT_TAPS.zip	5.3 KB
/.../Q91 Design Flow/Using Megafunctions/Memory Compiler/FIFO/
ug_fifo_partitioner.pdf	313.8 KB
/.../Q91 Design Flow/Using Megafunctions/Memory Compiler/Flash Memory/
ug_alt_ufm.pdf	1.1 MB
alt_ufm_DesignExample.qar	73.6 KB
alt_ufm_msim.zip	16.4 KB
/.../Q91 Design Flow/Using Megafunctions/Memory Compiler/LPM_Shiftreg/
lpm_shiftreg.pdf	961.2 KB
lpm_shiftreg_DesignExample_ex1.qar	86.3 KB
lpm_shiftreg_DesignExample_ex1.zip	81.7 KB
lpm_shiftreg_DesignExample_ex2.qar	77.0 KB
lpm_shiftreg_DesignExample_ex2.zip	72.0 KB
lpm_shiftreg_ex1_msim.zip	5.3 KB
lpm_shiftreg_ex2_msim.zip	3.8 KB
/.../RAM and ROM/
ug_ram_rom.pdf	905.1 KB
Internal_Memory_DesignExample.zip	33.4 KB
/.../SCFIFO and DCFIFO/
ug_fifo.pdf	457.5 KB
dcfifo_design_example.zip	33.9 KB
/.../Q91 Design Flow/Using Megafunctions/
Quartus II Development Software Literature.mht	341.5 KB
/.../Q91 Design Flow/
quartusii_handbook.pdf	28.9 MB
intro_to_quartus2.pdf	5.1 MB
mnl_qts_quick_start.pdf	549.5 KB
FPGA.mht	216.2 KB
/.../Converting a Hexadecimal Value to a Standard Logic Vector/
VHDL Converting a Hexadecimal Value to a Standard Logic Vector.mht	124.3 KB
/.../Creating a Hierarchical Design/
VHDL Creating a Hierarchical Design.mht	125.7 KB
/.../VHDL Arithmetic Functions/Adder_Subtractor/
VHDL Adder-Subtractor.mht	127.3 KB
add-sub-vhdl_readme_v1.0.txt	1.9 KB
addsub.zip	0.5 KB
/.../VHDL Arithmetic Functions/Behavioral Counter/
Feedback.mht	125.2 KB
/.../Carry Look-Ahead Adder/
VHDL Carry Look-Ahead Adder.mht	125.7 KB
/.../VHDL Arithmetic Functions/Down Counter/
VHDL Down Counter.mht	124.8 KB
/.../Ripple-Carry Adder/
VHDL Ripple-Carry Adder.mht	125.9 KB
/.../VHDL Bus and IO Functions/Bidirectional Bus/
VHDL Bidirectional Bus.mht	125.2 KB
/.../Tri-State Buses/
VHDLTri-State Buses.mht	124.4 KB
/.../Implementing OFDM Modulation and Demodulation/
Implementing OFDM Modulation and Demodulation.mht	150.9 KB
/.../Node Synchronization Design Example for Viterbi Decoder/
VHDL Node Synchronization Design Example for Viterbi Decoder.mht	162.5 KB
/.../VHDL Digital Signal Processing (DSP) Functions/Signed Multiplier/
VHDL Signed Multiplier.mht	126.9 KB
signed-multiplier-vhdl_readme_v1.0.txt	1.9 KB
signed_mult.zip	0.4 KB
/.../Signed Multiply-Accumulator/
VHDL Signed Multiply-Accumulator.mht	127.4 KB
signed-multiply-accumulator-vhdl_readme_v1.0.txt	1.9 KB
sig_altmult_accum.zip	0.5 KB
/.../Unsigned Multiplier with Registered IO/
VHDL Unsigned Multiplier with Registered I-O.mht	127.7 KB
unsigned-multiplier-vhdl_readme_v1.0.txt	1.9 KB
unsigned_mult.zip	0.5 KB
/.../Unsigned Multiply-Adder/
VHDL Unsigned Multiply-Adder.mht	128.0 KB
unsigned-multiply-adder-vhd_readme_v1.0.txt	1.9 KB
unsignedmult_add.zip	0.6 KB
/.../VHDL Template for Inferring DSP Blocks in Stratix III and IV FPGAs/
stx4_siv51004.pdf	1.2 MB
qts_qii51007.pdf	602.3 KB
stx3_siii51005.pdf	456.9 KB
VHDL Template for Inferring DSP Blocks in Stratix III and IV FPGAs.mht	126.7 KB
vhdl-template.zip	15.3 KB
vhdl-template-readme.txt	3.1 KB
/.../Counter with Synchronous Load/
VHDL Counter with Synchronous Load.mht	127.1 KB
counter-vhdl_readme_v1.0.txt	1.8 KB
count.zip	0.4 KB
/.../Instantiating a D Flipflop using lpm_dff/
VHDL Instantiating a D Flipflop using lpm_dff.mht	124.7 KB
/.../VHDL Logic Functions/Instantiating a DFFE/
Feedback.mht	124.5 KB
/.../Preventing Unintentional Latch Creation/
VHDL Preventing Unintentional Latch Creation.mht	127.3 KB
prevent-latch-vhdl_readme_v1.0.txt	1.8 KB
nolatch.zip	0.4 KB
/.../VHDL 8 x 64 Shift Register with Taps/
VHDL 8 x 64 Shift Register with Taps.mht	128.5 KB
/.../Cycle-Shared Dual-Port RAM/
VHDL Cycle-Shared Dual-Port RAM (CODEcsdpram-CODE).mht	125.4 KB
/.../Dual Clock Synchronous RAM/
VHDL Dual Clock Synchronous RAM.mht	128.5 KB
dual-clock-syncram-vhdl_readme_v1.0.txt	1.8 KB
ram_dual.zip	0.5 KB
/.../QDR SRAM Controller/
an349.pdf	406.9 KB
VHDL QDR SRAM Controller.mht	141.7 KB
8x64-shift-register-vhd_readme_v1.0.txt	1.8 KB
shift_8x64_taps.zip	0.5 KB
/.../Single Clock Synchronous RAM/
VHDL Single Clock Synchronous RAM.mht	128.6 KB
single-clock-syncram-vhdl_readme_v1.0.txt	1.8 KB
ram.zip	0.5 KB
/.../Single Clock Synchronous RAM with Asynchronous Read Address/
VHDL Single Clock Synchronous RAM with Asynchronous Read Address.mht	129.0 KB
single-clk-syncram-asyncrd-vhdl_readme_v1.0.txt	1.9 KB
single-clk-syncram-asyncrd.zip	0.5 KB
/.../ZBT SRAM Controller/
an329.pdf	169.3 KB
VHDL ZBT SRAM Controller.mht	144.9 KB
/Техническая документация/VHDL/
VHDL VHDL Home.mht	130.6 KB
/
91sp2_quartus_free.exe	2.0 GB
Total files 574