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848.1 MB |
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206.4 MB |
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1.9 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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Altium Designer 10/Content/HDLSim_AlteraVerilog.ModuleDescription |
0.1 KB |
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1.9 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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0.1 KB |
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1.9 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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0.1 KB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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184.5 MB |
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0.1 KB |
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18.5 KB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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0.1 KB |
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2.0 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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0.1 KB |
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848.1 MB |
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206.4 MB |
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2.3 GB |
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Altium Designer 10/Content/HDLSim_AlteraVerilog.ModuleDescription |
0.1 KB |
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18.5 KB |
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117.3 KB |
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184.5 MB |
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3.2 GB |
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/Altium Designer 10/Builds/27333/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/27333/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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0.1 KB |
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3.2 GB |
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Altium Designer 10/Builds/27333/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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Altium Designer 10/Builds/27333/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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3.2 GB |
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Altium Designer 10/Builds/27333/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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184.5 MB |
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2.3 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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2.4 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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2.4 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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2.4 GB |
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117.3 KB |
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184.5 MB |
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0.1 KB |
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2.3 GB |
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/Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/zip/HDLSim_AlteraVerilog.zip |
184.5 MB |
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Altium Designer 10/Builds/22033/HDLSim_AlteraVerilog/HDLSim_AlteraVerilog.ModuleBuild |
117.3 KB |
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18.5 KB |
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0.1 KB |
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