Verilog | 95BFCF9C5801DE809D20E6CA1DDE5BF9CAA8765A

Verilog

Name	verilog	DOWNLOAD Copy Link
Total Size	157.2 MB
Total Files	509
Hash	95BFCF9C5801DE809D20E6CA1DDE5BF9CAA8765A

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FPGA PROTOTYPING with verilog examples - spartan3-2008.pdf	18.8 MB
Digital Design - An Embedded Systems Approach Using Verilog.pdf	2.1 MB
FSM-Based Digital Design Using Verilog HDL.rar	3.4 MB
ch3_Timing_Overhead.pdf	916.1 KB
271clockingnotes.pdf	112.3 KB
blocking and non blocking.pdf	70.3 KB
Boston_FullParallelCase.pdf	74.1 KB
Springer - SystemVerilog for Verification.pdf	1.5 MB
(ebook) Electronics - Verilog Digital Design Synthesis.pdf	11.6 MB
Cadence Verilog Languaje and Simulation Course.pdf	2.1 MB
CummingsHDLCON2001_Verilog2001_rev1_3.pdf	67.8 KB
design through verilog - IEEE.pdf	2.3 MB
eBook.Verilog.VHDL.Golden.Reference.Guide.pdf	377.3 KB
IEEE_Standard_verilog_std_1364_1995.pdf	1.8 MB
Kluwer.Academic.The.Verilog.Hardware.Description.Language.Fifth.Edition.pdf	8.1 MB
Kluwer-_Digital_Computer_Arithmetic_Datapath_Design_Using_Verilog_HDL.pdf	631.6 KB
Principles of Verifiable RTL Design-verilog.pdf	2.1 MB
the_complete_verilog_book.pdf	6.3 MB
Verilog-2001_paper.pdf	209.3 KB
verilog blocking and non blocking.pdf	70.3 KB
Verilog HDL Synthesis A Practical Primer-J Bhasker.pdf	5.4 MB
Verilog HDL(Gate Level Design).pdf	1.2 MB
Verilog Quick Ref1.pdf	23.5 KB
Verilog Quickstart - Practical Guide to Simulation & Synthesis in Verilog (3rd Ed.).pdf	6.4 MB
verilog ref.pdf	3.2 MB
verilog_faq.pdf	17.6 MB
verilog-accelerating digital design.pdf	34.1 KB
VerilogHDLHandboook_Bucknell.pdf	81.9 KB
VerilogLangRefManual.pdf	2.7 MB
Wiley,.Verilog.Coding.for.Logic.Synthesis.(2003).Spy.pdf	1.3 MB
Writing successful description in Verilog.pdf	89.1 KB
Writing Testbenches using System Verilog.rar	2.8 MB
L03-Verilog-Design-Examples.pdf	2.4 MB
SystemC-Primer.pdf	6.6 MB
Verilog HDL Synthesis A Practical Primer.pdf	5.4 MB
Navabi_verilog_digital_systems_design_navabi.pdf	28.3 MB
sol manual - verilog - brown.rar	743.4 KB
/sol manual - verilog - brown/
sol3.pdf	205.7 KB
sol4.pdf	89.1 KB
sol5.pdf	84.0 KB
sol6.pdf	97.6 KB
sol7.pdf	73.2 KB
sol8.pdf	104.8 KB
sol9.pdf	134.4 KB
sol10.pdf	195.2 KB
sol11.pdf	62.6 KB
sol2.pdf	127.3 KB
/FSM-Based Digital Design Using Verilog HDL/
Appendix A.pdf	221.2 KB
Appendix C.pdf	415.8 KB
Appendix D.pdf	126.9 KB
Front Matter.pdf	140.5 KB
Index.pdf	82.4 KB
Chapter 1Introduction to Finite-State Machines and State Diagrams for the Design.pdf	236.9 KB
Chapter 2 Using State Diagrams to Control External Hardware Subsystems.pdf	178.5 KB
Chapter 3 Synthesizing Hardware from a State Diagram.pdf	262.5 KB
Chapter 4 Synchronous Finite-State Machine Designs.pdf	364.4 KB
Chapter 5 The One Hot Technique in Finite-State Machine Design.pdf	396.2 KB
Chapter 6 Introduction to Verilog HDL.pdf	233.1 KB
Chapter 7 Elements of Verilog HDL.pdf	328.6 KB
Chapter 8 Describing Combinational and Sequential Logic using Verilog HDL.pdf	555.2 KB
Chapter 9 Asynchronous Finite-State Machines.pdf	383.2 KB
Chapter 10 Introduction to Petri Nets.pdf	234.6 KB
Appendix B Counting and Shifting Circuit Techniques.pdf	221.2 KB
/Writing Testbenches using System Verilog/
1What is Verification.pdf	241.0 KB
2Verification Technologies.pdf	438.9 KB
3The Verification Plan.pdf	283.7 KB
4High-Level Modeling.pdf	494.9 KB
5Stimulus and Response.pdf	439.3 KB
6Architecting Testbenches.pdf	344.7 KB
7Simulation Management.pdf	293.8 KB
back-matter.pdf	302.3 KB
front-matter.pdf	211.1 KB
/Verilog-lab/
hdl.var	0.1 KB
.make_new.csh	0.9 KB
.make_do.csh	0.9 KB
cds.lib	0.1 KB
/Verilog-lab/lab8_sdf/
rpu_data.txt	3.2 KB
rpu_timing.scf	0.1 KB
hdl.var	0.1 KB
rpu_asic.v	1.1 KB
rpu_core.v	131.7 KB
rpu_pads.v	2.8 KB
rpu_test.v	2.3 KB
cds.lib	0.1 KB
rpu_timing.sdf	3.9 KB
/Verilog-lab/lab8_sdf/vloglib/
NR2P.v	0.3 KB
EO.v	0.3 KB
EN3.v	0.4 KB
FD1P.v	0.8 KB
EN.v	0.3 KB
MUX21L.v	0.4 KB
OR2.v	0.3 KB
AN4.v	0.4 KB
MUX31RLP.v	0.6 KB
AO2.v	0.5 KB
MUX41.v	0.7 KB
IV.v	0.2 KB
AO6.v	0.4 KB
FDS2.v	1.2 KB
MUX81.v	1.3 KB
AO4.v	0.5 KB
OPAD.v	0.2 KB
FDS2L.v	1.5 KB
AN3.v	0.4 KB
OR3P.v	0.4 KB
MUX31LP.v	0.6 KB
B4I.v	0.2 KB
MUX81P.v	1.3 KB
AO1.v	0.5 KB
SFD2P.v	1.2 KB
DELAY1.v	0.2 KB
AO3.v	0.5 KB
AN2.v	0.3 KB
ND3.v	0.4 KB
MUX21H.v	0.4 KB
MUX31H.v	0.6 KB
EO3.v	0.4 KB
OR2P.v	0.3 KB
ND2.v	0.3 KB
AO7.v	0.4 KB
MUX31RL.v	0.6 KB
IVA.v	0.2 KB
MUX21SP.v	0.4 KB
NR4.v	0.5 KB
NR2.v	0.3 KB
ND2P.v	0.3 KB
IPAD.v	0.2 KB
ND4.v	0.5 KB
MUX31L.v	0.6 KB
NR3.v	0.4 KB
BUF8A.v	0.2 KB
OR3.v	0.4 KB
B4IP.v	0.2 KB
NR5.v	0.5 KB
B2A.v	0.2 KB
IVP.v	0.2 KB
FD1.v	0.8 KB
IOPAD.v	0.4 KB
NR3P.v	0.4 KB
/Verilog-lab/lab8_sdf/sources/
constraints.tcl	1.5 KB
pre.f	0.1 KB
rpu_core.v	7.9 KB
rpu_core_hier.v	13.9 KB
post.f	0.1 KB
buildgates.tcl	1.6 KB
/Verilog-lab/solutions/lab6_gui/
results	0.4 KB
ncsim-rtl.log	1.0 KB
ncsim-gate.log	1.0 KB
ncsim-udp.log	1.0 KB
/Verilog-lab/solutions/lab8_sdf/
script	1.7 KB
results	1.6 KB
/Verilog-lab/solutions/lab3_alu/
results	0.5 KB
ncsim.log	0.7 KB
/Verilog-lab/solutions/lab1_mux/
results	0.3 KB
hdl.var	0.1 KB
cds.lib	0.0 KB
ncsim.log	0.2 KB
/Verilog-lab/solutions/lab2_rgs/
results	1.1 KB
hdl.var	0.1 KB
cds.lib	0.1 KB
ncsim.log	0.4 KB
/Verilog-lab/solutions/lab3_mem/
results	0.2 KB
ncsim.log	0.8 KB
/Verilog-lab/solutions/lab3_smx/
results	0.4 KB
ncsim.log	0.7 KB
/Verilog-lab/solutions/lab9_api/
Makefile_vhdl_native_runtime	11.0 KB
Makefile_vlog_native_shared_libs	10.9 KB
Makefile_vhdl_gcc_ccc_static	10.9 KB
Makefile_gcc_ccc_static	11.5 KB
Makefile_vlog_gcc_runtime	10.9 KB
Makefile-vhdl-ccc_static	10.3 KB
script	7.3 KB
results	3.8 KB
Makefile_vlog_gcc_shared_libs	10.9 KB
Makefile_native_dynamic	11.5 KB
Makefile_native_ccc_static	11.5 KB
Makefile_vlog_native_runtime	10.9 KB
Makefile_vhdl_gcc_shared_libs	10.9 KB
Makefile_vhdl_native_static	10.9 KB
Makefile_vhdl_native_ccc_static	10.9 KB
Makefile_gcc_shared_libs	11.5 KB
Makefile-vlog-ccc_static	10.3 KB
Makefile_vhdl_gcc_static	10.9 KB
Makefile_native_shared_libs	11.5 KB
Makefile_gcc_static	11.5 KB
Makefile_vlog_gcc_static	10.9 KB
Makefile_vhdl_native_dynamic	10.9 KB
Makefile_vhdl_gcc_runtime	10.9 KB
Makefile_gcc_dynamic	11.5 KB
Makefile_vhdl_native_shared_libs	11.0 KB
Makefile_vlog_native_dynamic	10.9 KB
Makefile_native_runtime	11.5 KB
Makefile_vlog_native_ccc_static	11.0 KB
Makefile_vhdl_gcc_dynamic	10.9 KB
Makefile_vlog_gcc_dynamic	10.9 KB
Makefile_gcc_runtime	11.5 KB
Makefile_native_static	11.5 KB
Makefile_vlog_native_static	10.9 KB
Makefile_vlog_gcc_ccc_static	11.0 KB
/Verilog-lab/solutions/lab2_cnt/
results	1.4 KB
hdl.var	0.2 KB
cds.lib	0.1 KB
ncsim.log	0.6 KB
/Verilog-lab/solutions/lab1_tut/
results	0.0 KB
/Verilog-lab/solutions/lab5_cpu/
results	1.2 KB
ncsim-rtl.log	4.6 KB
ncsim-gate.log	4.6 KB
ncsim-udp.log	4.6 KB
/.../ncsim-gate.shm/
ncsim.trn	1.5 KB
ncsim.dsn	2.4 KB
/.../ncsim-rtl.shm/
ncsim.trn	1.5 KB
ncsim.dsn	2.4 KB
/.../ncsim-udp.shm/
ncsim.trn	1.5 KB
ncsim.dsn	2.4 KB
/Verilog-lab/solutions/lab4_ctl/
results	0.3 KB
hdl.var	0.1 KB
my_ncsimrc	0.0 KB
ncsim.log	7.0 KB
/Verilog-lab/solutions/lab4_ctl/ncsim.shm/
ncsim.trn	0.8 KB
ncsim.dsn	2.1 KB
/Verilog-lab/solutions/lab7_mix/
script	2.1 KB
results	1.9 KB
ncsim-vlog.log	0.1 KB
ncsim-sc.log	0.1 KB
ncsim-vhdl.log	0.1 KB
/Verilog-lab/solutions/lab7_mix/lab7_mix/
script	2.1 KB
results	2.3 KB
ncsim-vlog.log	0.1 KB
ncsim-sc.log	0.1 KB
ncsim-vhdl.log	0.1 KB
/Verilog-lab/solutions/lab6_sae/
results	0.2 KB
mem_test.v	3.9 KB
/Verilog-lab/lab3_alu/
hdl.var	0.1 KB
alu.v	0.8 KB
cds.lib	0.1 KB
alu_test.v	1.7 KB
/Verilog-lab/lab3_alu/vloglib/
cells.v	2.7 KB
/Verilog-lab/lab1_mux/
mux_test.v	0.6 KB
mux.v	0.2 KB
/Verilog-lab/lab2_rgs/
rgs.v	0.2 KB
rgs_test.v	1.5 KB
/Verilog-lab/lab2_rgs/vloglib/
dff.vg	1.0 KB
dff.vu	1.0 KB
dff.vr	0.3 KB
/Verilog-lab/lab3_mem/
hdl.var	0.0 KB
mem_data.txt	1.6 KB
mem_test.v	4.0 KB
cds.lib	0.1 KB
mem.v	0.8 KB
mem_test_fixed.v	4.0 KB
/Verilog-lab/lab3_smx/
smx_test.v	1.4 KB
hdl.var	0.0 KB
cds.lib	0.1 KB
smx.v	0.4 KB
/Verilog-lab/lab9_api/
vpi_user.c	0.1 KB
hdl.var	0.0 KB
my_vpi.c	0.4 KB
my_pli.cc	0.5 KB
my_pli.c	0.4 KB
veriuser.c	0.3 KB
my_vpi.cc	0.5 KB
cds.lib	0.0 KB
my_mod.v	0.1 KB
/Verilog-lab/lab2_cnt/
cnt_test.v	1.9 KB
cnt.v	0.5 KB
/Verilog-lab/lab2_cnt/vloglib/
cells.v	2.9 KB
/Verilog-lab/lab1_tut/
README.txt	1.3 KB
/Verilog-lab/lab5_cpu/
run	1.5 KB
stop.tcl	0.3 KB
hdl.var	0.0 KB
CPUtest3.txt	1.7 KB
cpu_test.v	0.8 KB
cds.lib	0.1 KB
ncsim.tcl	0.3 KB
CPUtest1.txt	1.6 KB
CPUtest2.txt	1.4 KB
cpu.v	2.7 KB
.comparescan_rules	0.1 KB
/Verilog-lab/lab4_ctl/
hdl.var	0.0 KB
ctl.v	2.9 KB
ctl_test.v	8.2 KB
cds.lib	0.1 KB
/Verilog-lab/sources/lab6_gui/
.make_new.csh	0.1 KB
.make_do.csh	1.6 KB
/Verilog-lab/sources/lab8_sdf/
rpu_data.txt	3.2 KB
rpu_timing.scf	0.1 KB
hdl.var	0.1 KB
rpu_asic.v	1.1 KB
rpu_core.v	131.7 KB
.make_new.csh	0.1 KB
.make_do.csh	4.0 KB
rpu_pads.v	2.8 KB
rpu_test.v	2.3 KB
cds.lib	0.1 KB
rpu_timing.sdf	3.9 KB
/Verilog-lab/sources/lab8_sdf/vloglib/
NR2P.v	0.3 KB
EO.v	0.3 KB
EN3.v	0.4 KB
FD1P.v	0.8 KB
EN.v	0.3 KB
MUX21L.v	0.4 KB
OR2.v	0.3 KB
AN4.v	0.4 KB
MUX31RLP.v	0.6 KB
AO2.v	0.5 KB
MUX41.v	0.7 KB
IV.v	0.2 KB
AO6.v	0.4 KB
FDS2.v	1.2 KB
MUX81.v	1.3 KB
AO4.v	0.5 KB
OPAD.v	0.2 KB
FDS2L.v	1.5 KB
AN3.v	0.4 KB
OR3P.v	0.4 KB
MUX31LP.v	0.6 KB
B4I.v	0.2 KB
MUX81P.v	1.3 KB
AO1.v	0.5 KB
SFD2P.v	1.2 KB
DELAY1.v	0.2 KB
AO3.v	0.5 KB
AN2.v	0.3 KB
ND3.v	0.4 KB
MUX21H.v	0.4 KB
MUX31H.v	0.6 KB
EO3.v	0.4 KB
OR2P.v	0.3 KB
ND2.v	0.3 KB
AO7.v	0.4 KB
MUX31RL.v	0.6 KB
IVA.v	0.2 KB
MUX21SP.v	0.4 KB
NR4.v	0.5 KB
NR2.v	0.3 KB
ND2P.v	0.3 KB
IPAD.v	0.2 KB
ND4.v	0.5 KB
MUX31L.v	0.6 KB
NR3.v	0.4 KB
BUF8A.v	0.2 KB
OR3.v	0.4 KB
B4IP.v	0.2 KB
NR5.v	0.5 KB
B2A.v	0.2 KB
IVP.v	0.2 KB
FD1.v	0.8 KB
IOPAD.v	0.4 KB
NR3P.v	0.4 KB
/Verilog-lab/sources/lab8_sdf/sources/
constraints.tcl	1.5 KB
pre.f	0.1 KB
rpu_core.v	7.9 KB
rpu_core_hier.v	13.9 KB
post.f	0.1 KB
buildgates.tcl	1.6 KB
/Verilog-lab/sources/lab3_alu/
hdl.var	0.1 KB
.make_new.csh	0.1 KB
alu.v	0.8 KB
.make_do.csh	3.3 KB
cds.lib	0.1 KB
alu_test.v	1.7 KB
/Verilog-lab/sources/lab3_alu/vloglib/
cells.v	2.7 KB
/Verilog-lab/sources/lab1_mux/
mux_test.v	0.6 KB
mux.v	0.2 KB
.make_new.csh	0.1 KB
.make_do.csh	2.7 KB
/Verilog-lab/sources/lab2_rgs/
rgs.v	0.2 KB
.make_new.csh	0.1 KB
.make_do.csh	5.6 KB
rgs_test.v	1.5 KB
/Verilog-lab/sources/lab2_rgs/vloglib/
dff.vg	1.0 KB
dff.vu	1.0 KB
dff.vr	0.3 KB
/Verilog-lab/sources/lab3_mem/
hdl.var	0.0 KB
.make_new.csh	0.1 KB
mem_data.txt	1.6 KB
.make_do.csh	2.9 KB
mem_test.v	4.0 KB
cds.lib	0.1 KB
mem.v	0.8 KB
mem_test_fixed.v	4.0 KB
/Verilog-lab/sources/lab3_smx/
smx_test.v	1.4 KB
hdl.var	0.0 KB
.make_new.csh	0.1 KB
.make_do.csh	2.5 KB
cds.lib	0.1 KB
smx.v	0.4 KB
/Verilog-lab/sources/lab9_api/
vpi_user.c	0.1 KB
hdl.var	0.0 KB
my_vpi.c	0.4 KB
my_pli.cc	0.5 KB
my_pli.c	0.4 KB
.make_new.csh	0.1 KB
.make_do.csh	13.4 KB
veriuser.c	0.3 KB
my_vpi.cc	0.5 KB
cds.lib	0.0 KB
my_mod.v	0.1 KB
/Verilog-lab/sources/lab2_cnt/
cnt_test.v	1.9 KB
.make_new.csh	0.1 KB
.make_do.csh	5.4 KB
cnt.v	0.5 KB
/Verilog-lab/sources/lab2_cnt/vloglib/
cells.v	2.9 KB
/Verilog-lab/sources/lab1_tut/
README.txt	1.3 KB
.make_new.csh	0.1 KB
.make_do.csh	0.3 KB
/Verilog-lab/sources/lab5_cpu/
run	1.5 KB
stop.tcl	0.3 KB
hdl.var	0.0 KB
CPUtest3.txt	1.7 KB
cpu_test.v	0.8 KB
.make_new.csh	0.2 KB
.make_do.csh	4.1 KB
cds.lib	0.1 KB
ncsim.tcl	0.3 KB
CPUtest1.txt	1.6 KB
.register.sv	6.1 KB
CPUtest2.txt	1.4 KB
cpu.v	2.7 KB
.comparescan_rules	0.1 KB
/Verilog-lab/sources/lab4_ctl/
hdl.var	0.0 KB
.make_new.csh	0.1 KB
.make_do.csh	2.6 KB
ctl.v	2.9 KB
ctl_test.v	8.2 KB
cds.lib	0.1 KB
/Verilog-lab/sources/lab7_mix/
dff_test.vlog	1.0 KB
hdl.var	0.0 KB
dff.h.copy	0.3 KB
dff_test.h	0.5 KB
dff_test.vhdl	1.7 KB
.make_new.csh	0.1 KB
dff.vlog	0.2 KB
.make_do.csh	8.4 KB
dff_test.cpp	0.8 KB
cds.lib	0.1 KB
dff.vhdl	0.3 KB
dff.cpp.copy	0.1 KB
dff.cpp	0.1 KB
dff.h	0.3 KB
/Verilog-lab/sources/lab7_mix/lab7_mix/
dff_test.vlog	1.0 KB
hdl.var	0.0 KB
dff_test.h	0.5 KB
dff_test.vhdl	1.7 KB
.make_new.csh	0.1 KB
dff.vlog	0.2 KB
.make_do.csh	7.8 KB
dff_test.cpp	0.8 KB
cds.lib	0.1 KB
dff_copy.h	0.3 KB
dff.vhdl	0.3 KB
dff_copy.cpp	0.1 KB
dff.cpp	0.1 KB
dff.h	0.3 KB
/Verilog-lab/sources/lab6_sae/
.make_new.csh	0.1 KB
.make_do.csh	1.0 KB
mem_test.v	3.9 KB
mem.v	0.8 KB
/Verilog-lab/lab7_mix/
dff_test.vlog	1.0 KB
hdl.var	0.0 KB
dff.h.copy	0.3 KB
dff_test.h	0.5 KB
dff_test.vhdl	1.7 KB
dff.vlog	0.2 KB
dff_test.cpp	0.8 KB
cds.lib	0.1 KB
dff.vhdl	0.3 KB
dff.cpp.copy	0.1 KB
dff.cpp	0.1 KB
dff.h	0.3 KB
/Verilog-lab/lab7_mix/lab7_mix/
dff_test.vlog	1.0 KB
hdl.var	0.0 KB
dff_test.h	0.5 KB
dff_test.vhdl	1.7 KB
.make_new.csh	0.1 KB
dff.vlog	0.2 KB
.make_do.csh	7.8 KB
dff_test.cpp	0.8 KB
cds.lib	0.1 KB
dff_copy.h	0.3 KB
dff.vhdl	0.3 KB
dff_copy.cpp	0.1 KB
dff.cpp	0.1 KB
dff.h	0.3 KB
/Verilog-lab/lab6_sae/
mem_test.v	3.9 KB
mem.v	0.8 KB
/moving-sum/
moving-sum.pdf	55.0 KB
moving-sum.ps	246.8 KB
moving-sum.sav	0.3 KB
moving-sum.stems	0.6 KB
moving-sum.tex	9.6 KB
moving-sum.v	3.1 KB
moving-sum.vcd	5.0 KB
movsum-1.eps	28.9 KB
movsum-2.eps	31.8 KB
movsum-blocks.eps	9.9 KB
movsum-full-1.eps	35.8 KB
movsum-full-2.eps	40.1 KB
movsum-full.sav	0.5 KB
movsum-full.v	4.3 KB
movsum-full.vcd	6.1 KB
/runlength/
runlength-1.eps	25.5 KB
runlength-2.eps	25.7 KB
runlength.pdf	44.6 KB
runlength.sav	0.3 KB
runlength.stems	0.2 KB
runlength.tex	8.8 KB
runlength.v	4.6 KB
runlength.vcd	3.9 KB
Total files 509